Samsung S3C6400X User Manual page 960

MIPI HSI
Bits Name
[1] Brframe_end
[0] TxFIFO_empty
INTMSK_REG
INTMSK_REG is interrupt mask & DMA request enabler register.
Address = BASEADDR + 0x10 (0x7E00_6010)
Bits Name
[31] DMA_req_en
[30:5] Reserved
[4] TxH_timeout_ms
k
[3] TxI_timeout_msk TxIDLE state timeout interrupt mask
[2] TxR_timeout_ms
k
[1] Brframe_end_ms
k
[0] TxFIFO_empty_
msk
SWRST_REG
SWRST_REG is software reset.
Address = BASEADDR + 0x14 (0x7E00_6014)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-16
Specifications and information herein are subject to change without notice.
Description
Break frame transfer–done in Frame mode
(set '1' for clearing)
TxFIFO empty interrupt (set '1' for clearing)
Table 28-8 INTSRC_REG register description
Description
DMA request signal enable
0: enable
Reserved bits
TxHOLD state timeout interrupt mask
0 : unmask
0 : unmask
TxREQ state timeout interrupt mask
0 : unmask
Break frame transfer–done mask (in Frame mode)
0 : unmask
TxFIFO empty interrupt mask
0 : unmask
Table 28-9 INTMSK_REG register description
S3C6400X RISC MICROPROCESSOR
1: disable
1 : mask
1 : mask
1 : mask
1 : mask
1 : mask
R/W Reset Value
R/W 0x0
R/W 0x1
R/W Reset Value
R/W 0x1
R 0x0000000
R/W 0x1
R/W 0x1
R/W 0x1
R/W 0x1
R/W 0x1