Samsung S3C6400X User Manual page 925

S3C6400X RISC MICROPROCESSOR
[3]
This status is set if the Host Controller detects the Host DMA Buffer boundary
[2]
transaction is stopped at SD Bus timing. The Read Wait must be supported in
[1]
two cases in which this interrupt is generated. The first is when a data transfer
the Host System). The second is when data has stopped at the block gap and
setting Stop At Block Gap Request in the Block Gap Control register and data
This status is set if the Buffer Write Enable changes from 0 to 1. Refer to the
Buffer Write Enable in the Present State register. (RW1C)
during transfer. Refer to the Host DMA Buffer Boundary in the Block Size
register. Other DMA interrupt factors may be added in the future. This
interrupt cannot be generated after the Transfer Complete. (RW1C)
'1' = DMA Interrupt is generated
If the Stop At Block Gap Request in the Block Gap Control register is set, this
bit is set when both a read / write transaction is stopped at a block gap. If
Stop At Block Gap Request is not set to 1, this bit is not set to 1. (RW1C)
(1) In the case of a Read Transaction
This bit is set at the falling edge of the DAT Line Active Status (When the
(2) Case of Write Transaction
This bit is set at the falling edge of Write Transfer Active Status (After getting
CRC status at SD Bus timing).
'1' = Transaction stopped at block gap
This bit is set when a read / write transfer is completed.
(1) In the case of a Read Transaction
This bit is set at the falling edge of Read Transfer Active Status. There are
is completed as specified by data length (After the last data has been read to
completed the data transfer by setting the Stop At Block Gap Request in the
Block Gap Control register (After valid data has been read to the Host
(2) In the case of a Write Transaction
This bit is set at the falling edge of the DAT Line Active Status. There are two
cases in which this interrupt is generated. The first is when the last data is
written to the SD card as specified by data length and the busy signal
released. The second is when data transfers are stopped at the block gap by
transfers completed. (After valid data is written to the SD card and the busy
The table below shows that Transfer Complete has higher priority than
Data Timeout Error. If both bits are set to 1, the data transfer can be
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
'1' = Ready to write buffer
'0' = Not ready to write buffer
DMA Interrupt
'0' = No DMA Interrupt
Block Gap Event
order to use this function.
'0' = No Block Gap Event
Transfer Complete
System).
signal released). (RW1C)
considered complete.
HSMMC CONTROLLER
0
0
0
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