Samsung S3C6400X User Manual page 975

SPI CONTROLLER
TxChOn [0]
Register
Clk_CFG(Ch0) 0x7F00B004
Clk_CFG(Ch1) 0x7F00C004
Clk_CFG Bit
ClkSel [10:9]
ENCLK [8]
Prescaler [7:0]
Value
Register
MODE_CFG(Ch0)
MODE_CFG(Ch1)
MODE_CFG
Ch_tran_size
Trailing Count
BUS transfer size
RxTrigger
TxTrigger
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
29-6
Specifications and information herein are subject to change without notice.
R/W SPI Tx Channel On
0: Channel Off
Address R/W
R/W Clock configuration register
R/W Clock configuration register
R/W Clock source selection to generate SPI clock-out
00 : PCLK
10 : Epll clock
*
For using USBCLK source, The USB_SIG_MASK at
system controller must be set to on.
R/W
Clock on/off
0 : disable
R/W
SPI clock-out division rate
SPI clock-out =
Address R/W
0x7F00B008 R/W
0x7F00C008 R/W
Bit
[30:29] R/W
[28:19] R/W
00: byte
[18:17] R/W
10 : word
R/W Rx FIFO trigger level in INT mode. Trigger
[16:11]
level is from 6'h0 to 6'h40. The value means
byte number in RX FIFO
R/W
[10:5] Tx FIFO trigger level in INT mode
Trigger level is from 6'h0 to 6'h40. The value
means byte number in TX FIFO
1: Channel On
Description
Description
01 : USBCLK
11 : reserved
Clock source / ( 2 x (Prescaler value +1))
Description
SPI FIFO control register
SPI FIFO control register
Description
00 : Byte
10 : word
Count value from writing the last data in RX
FIFO to flush trailing bytes in FIFO
01: halfword
11:reserved
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
1 : enable
Reset Value
Initial State
01 : Halfword
11 : reserved
1'b0
0x0
0x0
2'b0
1'b0
8'h0
0x0
0x0
2'b0
10'b0
2'b0
6'b0
6'b0