Samsung S3C6400X User Manual page 298

DMA
peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists.
Hardware DMA channels priority. Each DMA channel has a specific hardware priority. DMA channel 0
has the highest priority down to channel 7 which has the lowest priority. If requests from two channels
become active at the same time the channel with the highest priority is serviced first.
The DMAC is programmed by writing to the DMA control registers over the AHB slave interface.
Two AXI bus masters pass through AHBtoAXI bridges for transferring data. These interfaces are used
to transfer data when a DMA request goes active.
Incrementing or non-incrementing address for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to increase efficiency of
transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral.
Internal four word FIFO per channel.
Supports 8, 16 and 32-bit wide transactions.
Big-endian and little-endian support. The DMA controller defaults to little-endian mode on reset.
Separate and combined DMA error and DMA count interrupt requests. An interrupt to the processor
can be generated on a DMA error or when a DMA count has reached 0 (this is usually used to indicate
that a transfer has finished). Three interrupt request signals are used to do this:
— DMACINTTC signals when a transfer has completed.
— DMACINTERR signals when an error has occurred.
— DMACINTR combines both the DMACINTTC and DMACINTERR interrupt request signals. The
DMACINTR interrupt request can be used in systems, which have few interrupt controller request
inputs.
Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking.
Preliminary product information describe products that are in development,
11-2
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
S3C6400 RISC MICROPROCESSOR