Samsung S3C6400X User Manual page 310

DMA
Name
DMACSoftBReq
DMACSoftSReq
DMACSoftLBReq
DMACSoftLSReq
DMACConfiguration
DMACSync
DMACC0SrcAddr
DMACC0DestAddr
DMACC0LLI
DMACC0Control0
DMACC0Control1
DMACC0Configuration
DMACC1SrcAddr
DMACC1DestAddr
DMACC1LLI
DMACC1Control0
DMACC1Control1
DMACC1Configuration
DMACC2SrcAddr
DMACC2DestAddr
DMACC2LLI
DMACC2Control0
DMACC2Control1
DMACC2Configuration
DMACC3SrcAddr
DMACC3DestAddr
DMACC3LLI
DMACC3Control0
DMACC3Control1
DMACC3Configuration
Preliminary product information describe products that are in development,
11-14
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 11-1 DMA register summary (continued)
Type Width
R/W 16 This register allows DMA burst requests to be
generated by software.
R/W 16 This register allows DMA single requests to be
generated by software.
R/W 16 This register allows DMA last burst requests to
be generated by software.
R/W 16 This register allows DMA last single requests to
be generated by software.
R/W 3 This register is used to configure the DMA
controller.
R/W 16 This register enables or disables synchronization
logic for the DMA request signals.
R/W 32 DMA channel 0 source address.
R/W 32 DMA channel 0 destination address.
R/W 32 DMA channel 0 linked list address.
R/W 32 DMA channel 0 control0.
R/W 32 DMA channel 0 control1.
R/W 19 DMA channel 0 configuration register.
R/W 32 DMA channel 1 source address.
R/W 32 DMA channel 1 destination address.
R/W 32 DMA channel 1 linked list address.
R/W 32 DMA channel 1 control0.
R/W 32 DMA channel 1 control1.
R/W 19 DMA channel 1 configuration register.
R/W 32 DMA channel 2 source address.
R/W 32 DMA channel 2 destination address.
R/W 32 DMA channel 2 linked list address.
R/W 32 DMA channel 2 control.
R/W 32 DMA channel 2 control.
R/W 19 DMA channel 2 configuration register.
R/W 32 DMA channel 3 source address.
R/W 32 DMA channel 3 destination address.
R/W 32 DMA channel 3 linked list address.
R/W 32 DMA channel 3 control0.
R/W 32 DMA channel 3 control1.
R/W 19 DMA channel 3 configuration register.
S3C6400 RISC MICROPROCESSOR
Description Offset Reset Value
0x020 0x0000
0x024 0x0000
0x028 0x0000
0x02C 0x0000
0x030 0x000
0x034 0x0000
0x100 0x00000000
0x104 0x00000000
0x108 0x00000000
0x10C 0x00000000
0x110 0x00000000
0x114 0x00000
0x120 0x00000000
0x124 0x00000000
0x128 0x00000000
0x12C 0x00000000
0x130 0x00000000
0x134 0x00000
0x140 0x00000000
0x144 0x00000000
0x148 0x00000000
0x14C 0x00000000
0x150 0x00000000
0x154 0x00000
0x160 0x00000000
0x164 0x00000000
0x168 0x00000000
0x16C 0x00000000
0x170 0x00000000
0x174 0x00000