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POST PROCESSOR
Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr
Register
Address
Offset_oCb
0x77000084
Register
Address
Offset_oCr
0x77000088
Next Frame DMA Start Address Register for Output Cb and Cr
Register
NxtADDRStart_oCb
Register
NxtADDRStart_oCr
Preliminary product information describe products that are in development,
15-30
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
Bit
R/W
[23:0]
R/W
Bit
R/W
[23:0]
Address
R/W
0x7700008C
R/W
Address
R/W
0x77000090
R/W
Description
Offset of Cb component for fetching
destination image (For more information
refer to chapter 15-4)
Description
Offset of Cr component for fetching
destination image (For more information
refer to chapter 15-4)
Bit
Description
Next Frame DMA (Buffer 1) Start
[30:0]
address for destination Cb component
Bit
Description
Next Frame DMA (Buffer 1) Start
[30:0]
address for destination Cr component
S3C6400X RISC MICROPROCESSOR
Reset Value
Reset Value
Reset Value
0x20006300
Reset Value
0x20006300
0x0
0x0
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