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TV SCALER
MODE Control Register 2
Register
MODE_2
MODE_2
Bit
FIFO_OUT_PA
[6:5]
TH
ADDR_CH_DIS
[4]
BC_SEL
[3]
Reserved
[2:1]
TRG_MODE
[0]
Preliminary product information describe products that are in development,
16-32
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Address
R/W
0x763000A0
R/W
FIFO output path selection
00 = TV Encoder output
01 = FIMD WIN1
1x = FIMD WIN2
Next Address Change Disable in Free Run Mode (Software Trigger Mode)
When the current frame is completely finished and ADDR_CH_DIS is 0,
Next frame address set of NxtADDRXXX is copied into the current frame
address set of ADDRXXX. But if ADDR_CH_DIS is 1, ADDRXXX is not
changed. (For more information refer to chapter 16-5.2)
0 = Address Change Enable
1 = Address Change Disable
DMA address Change Selection ( Software Trigger Mode )
0 = Address change at EVEN/ODD FIELD end
1 = Address change at FRAME end
Must be set to '0'.
Select Enable DMA Processing Mode
0 : Software Trigger Mode
1 : reserved
S3C6400X RISC MICROPROCESSOR
Description
Mode Register 2
Description
Reset Value
0x0
Initial
State
00
0
0
0
0
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