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S3C6400X RISC MICROPROCESSOR
Burst Write
STAT[15:8] < (BLEN + 3) / 2
BLEN times
Burst Read
Read STAT
CTRL
RW= Write , BLEN>1
hDATA
a 32-bit address
hDATA
a 32-bit data
Figure 24-6. Burst Write Procedure
Figure 24-7. Burst Read Procedure
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Change Bank (BSEL
Select Bank 0)
Change Bank (BSEL
Select Bank 8)
Single Burst Packet is sent from Write_FIFO
HOST INTERFACE
24-7
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