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S3C6400 RISC MICROPROCESSOR
RS-232C INTERFACE
To connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI
signals are needed. In this case, you can control these signals with general I/O ports by software because the
AFC does not support the RS-232C interface.
INTERRUPT/DMA REQUEST GENERATION
Each UART of the S3C6400 has seven status (Tx/Rx/Error) signals: Overrun error, Parity error, Frame error,
Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty. All seven status signals
are indicated by the corresponding UART status register (UTRSTATn/UERSTATn).
The overrun error, parity error, frame error and break condition are referred as the receive error status. Each of
which can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to
one in the control register, UCONn. When a receive-error-status-interrupt-request is detected, the signal causing
the request can be identified by reading the value of UERSTSTn.
When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the
number of received data reaches Rx FIFO Trigger Level, Rx interrupt is generated. Rx interrupt is generated if
Receive mode in control register (UCONn) is selected as 1 (Interrupt request or polling mode).
In the Non-FIFO mode, transferring the data of the receive shifter to the receive holding register will cause Rx
interrupt under the Interrupt request and polling mode.
When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data
left in transmit FIFO reaches Tx FIFO Trigger Level, Tx interrupt is generated. Tx interrupt is generated if
Transmit mode in control register is selected as Interrupt request or polling mode.
In the Non-FIFO mode, transferring data from the transmit holding register to the transmit shifter will cause Tx
interrupt under the Interrupt request and polling mode.
Note that the Tx interrupt is always requested whenever the number of data in the transmit FIFO is smaller than
the trigger level. This means that an interrupt is requested as soon as you enable the Tx interrupt unless you fill
the Tx buffer prior to that. It is recommended to fill the Tx buffer first and then enable the Tx interrupt.
The interrupt controllers of S3C6400 are level-triggered type. You must set the interrupt type as 'Level' whenever
you program the UART control registers.
If the Receive mode and Transmit mode in control register are selected as the DMAn request
request occurs instead of Rx or Tx interrupt in the situation mentioned above.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART
mode,
then DMAn
31-5
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