Samsung S3C2451X User Manual

Risc microprocessor

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- Ac_Bit_Clk
- Ac_Sdi
- Sd0_Clk
- Sd0_Cmd
- Sd0_Dat0
- Sd0_Dat1
- Sd0_Dat2
- Sd0_Dat3
- Pcm0_Cdclk
- Pcm0_Sclk
  - Sd1_Clk
  - Sd1_Cmd
  - Sd1_Dat7
  - Sd1_Dat6
  - Sd1_Dat5
  - Sd1_Dat4
  - Sd1_Dat3
  - Sd1_Dat2
  - Sd1_Dat1
  - Sd1_Dat0
  - Pcm1_Sdo
  - Pcm1_Sdi
  - Pcm1_Cdclk
  - Pcm1_Sclk
- Pcm0_Sdi
- Pcm0_Sdo

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USER'S MANUAL

S3C2451X

RISC Microprocessor

June 11, 2008

Preliminary REV 0.10

Confidential Proprietary of Samsung Electronics Co., Ltd

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Summary of Contents for Samsung S3C2451X

Page 1 USER'S MANUAL S3C2451X RISC Microprocessor June 11, 2008 Preliminary REV 0.10 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved...
Page 2 Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 3 Revision History Revision No Description of Change Refer to Author(s) Date 0.00 - Initial Release (Preliminary) AP app part. May 26, 2008 0.10 Overview, DRAMC, IOport, TSADC, Electrical AP app part. June 11, 2008 Data updated. S3C2451X_USER’S MANUAL_PRELIMINARY_REV 0.10...
Page 4 NOTES S3C2451X_USER’S MANUAL_REV 0.10...
Page 5 To reduce total system cost, the S3C2451X includes the following components. The S3C2451X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier. Its low- power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
Page 6 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR FEATURES Architecture NAND Flash Boot Loader • • Integrated system for hand-held devices and Supports booting from NAND flash memory. general embedded applications. (Only 8bit boot support) • • 16/32-Bit RISC architecture and powerful 64KB for internal SRAM Buffer(8KB internal instruction set with ARM926EJ CPU core.
Page 7 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW FEATURES (Continued) Interrupt Controller LCD Controller • • 77 Interrupt sources Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette (One Watch dog timer, 5 timers, 12 UARTs, 24 color displays for color external interrupts, 8 DMA, 2 RTC, 2 ADC, 1 IIC, •...
Page 8 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR FEATURES (Continued) A/D Converter & Touch Screen Interface main shift clock • • Input (16bit 32depth) and output(16bit 32depth) 10-ch multiplexed ADC FIFOs to buffer data • Max. 500KSPS and 12-bit Resolution USB Host •...
Page 9 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW BLOCK DIAGRAM Figure 1-1. S3C2451X Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 10 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR PIN ASSIGNMENTS Figure 1-2. S3C2451X Pin Assignments (380-FBGA 0.65mm pitch) Top view Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 11 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 380-Pin FBGA Pin Assignments – Pin Number Order (1/4) Pin Name Ball Pin Name Ball Pin Name Ball RSMCLK/GPA23 CAMDATA1/GPJ1 VDDiarm RSMVAD/GPA24 CAMDATA2/GPJ2 RSMBWAIT/GPM0 D3 VDDi RGB_VD10/GPD2 nRCS3/GPA14 RGB_VD11/GPD3 nRCS4/GPA15 VDD_CAM RGB_VD12/GPD4 nRCS5/GPA16...
Page 12 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR RDATA9 RGB_VSYNC/GPC3 TOUT3/GPB3 RDATA8 GPC5 TCLK/GPB4 RDATA7 GPC6 nXBACK/GPB5 RDATA6 GPC7 nXBREQ/RTCK/GPB6 nXDACK1/I2CSDA1/ RDATA5 RGB_VD0/GPC8 GPB7 nXDREQ1/I2CSCL1/ RDATA4 RGB_VD1/GPC9 GPB8 nXDACK0/I2SSDO_1 RDATA3 RGB_VD2/GPC10 /GPB9 RDATA2 RGB_VD3/GPC11 VDDiarm RDATA1 RGB_VD4/GPC12 nXDREQ0/I2SSDO_2 RDATA0 RGB_VD5/GPC13 /GPB10 EXTUARTCLK/ CAMVSYNC/GPJ9 K7...
Page 13 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 380-Pin FBGA Pin Assignments – Pin Number Order (2/4) Pin Name Ball Pin Name Ball Pin Name Ball I2SCDCLK/GPE2/ RXD0/GPH1 AC_BIT_CLK/PCM0_ SD1_DAT[1]/GPL1 Y13 CDCLK I2SSDI/GPE3/ SD1_DAT[2]/GPL2 P13 nCTS1/GPH10 AC_SDI/PCM0_SDI I2SSDO_0/GPE4/ SD1_DAT[3]/GPL3 AA14 nRTS1/GPH11...
Page 14 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR I2SLRCK/GPE0/ AC_nRESET/PCM AIN5 0_FSYNC I2SSCLK/GPE1/ AC_SYNC/PCM0_ SD1_DAT[0]/GPL0 AIN4 AA19 SCLK Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 1-10 Specifications and information herein are subject to change without notice.
Page 15 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 380-Pin FBGA Pin Assignments – Pin Number Order (3/4) Pin Name Ball Pin Name Ball Pin Name Ball AIN3 nRSTOUT VDD_SDRAM AIN2 EINT8/GPG0 AIN1 EINT9/GPG1 SDATA15 AIN0 EINT10/GPG2 SDATA14 Vref EINT11/GPG3 SDATA13 VDDA_ADC...
Page 16 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR EINT7/GPF7 SDATA28/GPK12 nSCS[0] PWR_EN SDATA27/GPK11 nSCS[1] BATT_FLT SDATA26/GPK10 nSWE NRESET VDDi SCLK VDD_OP1 VDDi SDATA25/GPK9 VDDalive SDATA24/GPK8 nSCLK SDATA23/GPK7 SCKE SDATA22/GPK6 nSRAS SDATA21/GPK5 nSCAS SDATA20/GPK4 SADDR0 SDATA19/GPK3 SADDR1 nTRST SDATA18/GPK2 SADDR2 SDATA17/GPK1 SADDR3 SDATA16/GPK0 SADDR4 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 17 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1. 380-Pin FBGA Pin Assignments – Pin Number Order (4/4) Pin Name Ball Pin Name Ball Pin Name Ball SADDR5 RADDR13 VDD_SDRAM RADDR12 RADDR11 SADDR6 RADDR10 SADDR7 VDD_SRAM SADDR8 SADDR9 RADDR9 VSSA_ADC SADDR10 RADDR8...
Page 18 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR RADDR18/GPA3 VDDi RADDR17/GPA2 RADDR16/GPA1 RADDR15 RADDR14 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 1-14 Specifications and information herein are subject to change without notice.
Page 19 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2. S3C2451X 380-Pin FBGA Pin Assignments Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type RSMCLK/GPA23 RSMCLK O(L) pvhbsudtbrt RSMVAD/GPA24 RSMVAD O(H) pvhbsudtbrt RSMBWAIT/GPM0 RSMBWAIT pvhbsudtbrt nRCS3/GPA14 nRCS3 O(H) pvhbsudtbrt nRCS4/GPA15 nRCS4...
Page 20 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type CAMPCLK/GPJ8 GPJ8 pvhbsudtart CAMDATA0/GPJ0 GPJ0 pvhbsudtart CAMDATA1/GPJ1 GPJ1 pvhbsudtart CAMDATA2/GPJ2 GPJ2 pvhbsudtart VDDi VDDi vddivh_alv vssipvh_alv VDD_CAM VDD_SRAM vddtvh_alv vsstvh_alv CAMDATA3/GPJ3 GPJ3 pvhbsudtart CAMDATA4/GPJ4...
Page 21 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type RGB_VD7/GPC15 GPC15 pvhbsudtart RGB_VD8/GPD0 GPD0 pvhbsudtart RGB_VD9/GPD1 GPD1 pvhbsudtart VDDiarm VDDiarm vddicvlh_alv vssicvlh_alv RGB_VD10/GPD2 GPD2 pvhbsudtart RGB_VD11/GPD3 GPD3 pvhbsudtart RGB_VD12/GPD4 GPD4 pvhbsudtart RGB_VD13/GPD5 GPD5...
Page 22 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type VDDiarm VDDiarm vddicvlh_alv vssicvlh_alv nXDREQ0/GPB10/I2SSD GPB10 pvhbsudtart EXTUARTCLK/GPH12 GPH12 pvhbsudtart nCTS0/GPH8 GPH8 pvhbsudtart nRTS0/GPH9 GPH9 pvhbsudtart TXD0/GPH0 GPH0 pvhbsudtart RXD0/GPH1 GPH1 pvhbsudtart nCTS1/GPH10 GPH10...
Page 23 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type I2SSCLK/GPE1/AC_SYN -/-/- GPE1 pvhbsudtart C/PCM0_SCLK I2SCDCLK/GPE2/ -/-/- AC_BIT_CLK0/PCM0_CD GPE2 pvhbsudtart I2SSDI/GPE3/AC_SDI0/P -/-/- GPE3 pvhbsudtart CM0_SDI I2SSDO_0/GPE4/AC_SD -/-/- GPE4 pvhbsudtart O0/PCM0_SDO SPIMISO0/GPE11 GPE11 pvhbsudtart SPIMOSI0/GPE12...
Page 24 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type SD1_DAT[5]/GPL5/I2S1_ GPL5 pvhbsudtart CDCLK/PCM1_CDCLK SD1_DAT[6]/GPL6/I2S1_ GPL6 pvhbsudtart SDI/PCM1_SDI SD1_DAT[7]/GPL7/I2S1_ GPL7 pvhbsudtart SDO/PCM1_SDO SD0_CLK/GPE5 GPE5 -/-/- pvhbsudtart SD0_CMD/GPE6 GPE6 -/-/- pvhbsudtart SD0_DAT[0]/GPE7 GPE7 -/-/- pvhbsudtart...
Page 25 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type OM[1] OM[1] pvhbsudtart_alv OM[0] OM[0] pvhbsudtart_alv VDDi VDDi vddicvlh_alv vssicvlh_alv EXTCLK EXTCLK pvhbsudtart XTIpll XTIpll pvhsoscbrt XTOpll XTOpll pvhsoscbrt EINT0/GPF0 GPF0 pvhbsudtart_alv EINT1/GPF1 GPF1...
Page 26 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type EINT12/GPG4 GPG4 -/-/- pvhbsudtart_alv EINT13/GPG5 GPG5 pvhbsudtart_alv EINT14/GPG6 GPG6 pvhbsudtart_alv EINT15/GPG7 GPG7 pvhbsudtart_alv VDD_USBOS VDD_USBOSC vddtvh_alv VSS33C VSS33C vsstvh_alv XO_UDEV XO_UDEV pvhsoscbrt XI_UDEV XI_UDEV...
Page 27 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type vsstvm_alv SDATA15 SDATA15 Hi-z pvmbsudtbrt SDATA14 SDATA14 Hi-z pvmbsudtbrt SDATA13 SDATA13 Hi-z pvmbsudtbrt SDATA12 SDATA12 Hi-z pvmbsudtbrt SDATA11 SDATA11 Hi-z pvmbsudtbrt SDATA10 SDATA10 Hi-z...
Page 28 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type SADDR1 SADDR1 O(L) pvmbsudtbrt SADDR2 SADDR2 O(L) pvmbsudtbrt SADDR3 SADDR3 O(L) pvmbsudtbrt SADDR4 SADDR4 O(L) pvmbsudtbrt SADDR5 SADDR5 O(L) pvmbsudtbrt VDD_SDRAM VDD_SDRAM vddtvm_alv vsstvm_alv...
Page 29 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type RADDR13 RADDR13 O(L) pvhbsudtbrt RADDR12 RADDR12 O(L) pvhbsudtbrt RADDR11 RADDR11 O(L) pvhbsudtbrt RADDR10 RADDR10 O(L) pvhbsudtbrt VDD_SRAM VDD_SRAM vddtvh_alv vsstvh_alv RADDR9 RADDR9 O(L) pvhbsudtbrt...
Page 30 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Default I/O State I/O State Numbe Name Function @Sleep @nRESET Type VSSA_ADC VSSA_ADC VSSA_ADC VSSA_ADC VDDA_ADC VDDA_ADC NOTES: The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master.
Page 31 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW TABLE 1-3. I/O CELL TYPES AND DESCRIPTIONS Interface CMOS Retention Pull-up Pull-down Cell Name Ftn. Driver Strength Voltage /Schmitt /Control /Control Pvhbdc 1.8/2.5/3.3V analog Pvhbr 1.8/2.5/3.3V analog pvhbsudtart 1.8/2.5/3.3V Schmit 2.6/5.2/7.8/10.5mA pvhbsudtart_alv 1.8/2.5/3.3V Schmit 2.6/5.2/7.8/10.5mA pvhbsudtbrt 1.8/2.5/3.3V...
Page 32 ARMCLK, HCLK, PCLK. nRESET nRESET suspends any operation in progress and places S3C2451X into a known reset state. For a reset, nRESET must be held to L level for at least 4 OSCin after the processor power has been stabilized.
Page 33 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Signal In/Out Description current bus cycle cannot be completed. If nWAIT signal isn’t used in your system, nWAIT signal must be tied on pull-up resistor. SDRAM I/F SADDR[15:0] SDRAM Address bus SDATA[31:0] SDRAM Data Bus...
Page 34 (Bus Hold Request) allows another bus master to request control of the local bus. nXBACK active indicates that bus control has been granted. nXBACK nXBACK (Bus Hold Acknowledge) indicates that the S3C2451X has surrendered control of the local bus to another bus master. UART RXD[3:0] UART receives data input (ch.
Page 35 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Signal In/Out Description IICSCL IIC-bus clock IICSDA1 IIC-bus data IICSCL1 IIC-bus clock IIS-Multi Audio Interface I2SLRCK IIS-bus channel select clock I2SSCLK IIS-bus serial clock I2SCDCLK CODEC system clock I2SSDI IIS-bus serial data input I2SSDO IIS-bus serial data output(Front Left, Right)
Page 36 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Signal In/Out Description DP_UDEV DATA(+) for USB peripheral. REXT External Resistor ( 44.2ohm +/- 1%) XO_UDEV Crystal output XI_UDEV Crystal input SPIMISO[1:0] SPIMISO is the master data input line, when SPI is configured as a master.
Page 37 S3C2451X ROM/SRAM I/O Power VDD_OP1 S3C2451X System I/O Power 1 (2.5 ~ 3.3V) VDD_OP2 S3C2451X System I/O Power 2 ( 1.8 ~ 3.3V) VDD_OP3 S3C2451X System I/O Power 3 ( 1.8 ~ 3.3V) VDD_CAM S3C2451X Camera I/O Power (1.8 ~ 3.3V) VDD_LCD S3C2451X LCD I/O Power (2.5 ~ 3.3V)
Page 38 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR S3C2451X OPERATION MODE DESCRIPTION Table 1-5. S3C2451X Operation Mode Description Operation OM[4] OM[3] OM[2] OM[1] OM[0] OM[4] OM[3] OM[2] OM[1] OM[0] Mode addr(4) page(4K) addr(5) Large NAND Block addr(4) page(2K) addr(5) iROM iROM Reserved Reserved...
Page 39 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW S3C2451X MEMORY MAP AND BASE ADDRESS OF SPECIAL REGISTERS Memory Map SRAM SRAM SRAM (64KB) (64KB) (8KB) 0x40000_0000 SDRAM SDRAM SDRAM (nSCS1) (nSCS1) (nSCS1) MPORT1 0x3800_0000 SDRAM SDRAM SDRAM (nSCS0) (nSCS0) (nSCS0) 0x3000_0000 SROM SROM...
Page 40 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Table 1-6. Base Address of Special Registers Address Module Address Module 0x4E00_0000 NFCON 0x5E00_0000 Reserved 0x4D80_0000 CAM I/F 0x5D00_0000 Reserved 0x4D40_8000 0x5C00_0100 PCM1 0x4D00_0000 Reserved 0x5C00_0000 PCM0 0x4C80_0000 0x5B00_0000 AC97 0x4C00_0000 SYSCON 0x5A00_0000 Reserved 0x4B80_0000...
Page 41 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-7. S3C2451X Special Registers Acc. Read/ Register Name Address Reset Value Function Unit Write DRAM Controller BANKCFG 0x48000000 0x00099F0D Mobile DRAM configuration register BANKCON1 0x48000004 0x00000008 Mobile DRAM control register BANKCON2 0x48000008 0x00000008 Mobile DRAM timing control register...
Page 42 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write Bank3 output enable assertion delay SMBWSTOENR3 0x4F00006C 0x00000002 control register Bank4 output enable assertion delay SMBWSTOENR4 0x4F00008C 0x00000002 control register Bank5 output enable assertion delay...
Page 43 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write Bank5 burst read wait delay control SMBWSTBRDR5 0x4F0000BC 0x0000001F register SMBONETYPER 0x4F000100 SMC Bank OneNAND TYPE SELECTION REGISTER SMCSR 0x4F000200 0x00000000 SMC status register SMCCR...
Page 44 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write ATA_STATUS 0x4B801904 0x00000000 ATA status ATA_COMMAND 0x4B801908 0x00000000 ATA command ATA_SWRST 0x4B80190C 0x00000000 ATA software reset ATA_IRQ 0x4B801910 0x00000000 ATA interrupt sources ATA_IRQ_MASK 0x4B801914 0x0000001F...
Page 45 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write STATUS USB Host Controller HcRevision 0x49000000 Control and status group HcControl 0x49000004 HcCommonStatus 0x49000008 HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInterruptDisable 0x49000014 HcHCCA 0x49000018 Memory pointer group...
Page 46 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write DISRC1 0x4B000100 DMA 1 initial source DISRCC1 0x4B000104 DMA 1 initial source control DIDST1 0x4B000108 DMA 1 initial destination DIDSTC1 0x4B00010C DMA 1 initial destination control...
Page 47 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write DCSRC4 0x4B000418 DMA 4 current source DCDST4 0x4B00041C DMA 4 current destination DMASKTRIG4 0x4B000420 DMA 4 mask trigger DMAREQSEL4 0x4B000424 DMA4 Request Selection Register DISRC5...
Page 48 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write LOCKCON1 0x4C00_0004 0x0000_FFFF EPLL lock time count register OSCSET 0x4C00_0008 0x0000_8000 Oscillator stabilization control register MPLLCON 0x4C00_0010 0x0185_40C0 MPLL configuration register EPLLCON 0x4C00_0018 0x0120_0102 EPLL configuration register...
Page 49 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write VIDOSD0A 0x4C80_0028 0x0000_0000 Video Window 0’s position control register VIDOSD0B 0x4C80_002C 0x0000_0000 Video Window 0’s position control register VIDOSD1A 0x4C80_0034 0x0000_0000 Video Window 1’s position control...
Page 50 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write WIN0MAP 0x4C80_00D0 0x0000_0000 Window color control WIN1MAP 0x4C80_00D4 0x0000_0000 Window color control WPALCON 0x4C80_00E4 0x0000_0000 Window Palette control register SYSIFCON0 0x4C80_0130 0x0000_0000 System Interface control for Main LDI...
Page 51 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write NFM8ECC0 0x4E000050 Generated 8-bit ECC status0 register NFM8ECC1 0x4E000054 Generated 8-bit ECC status1 register NFM8ECC2 0x4E000058 Generated 8-bit ECC status2 register NFM8ECC3 0x4E00005C Generated 8-bit ECC status3 register...
Page 52 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write CICOSCCTRL 0x4D80_0058 Codec main-scaler control CICOTAREA 0x4D80_005C Codec scaler target area CICOSTATUS 0x4D80_0064 Codec path status CIPRCLRSA1 0x4D80_006C RGB 1st frame start address for preview DMA...
Page 53 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write UMCON0 0x5000000C UART 0 modem control UTRSTAT0 0x50000010 UART 0 Tx/Rx status UERSTAT0 0x50000014 UART 0 Rx error status UFSTAT0 0x50000018 UART 0 FIFO status...
Page 54 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write UTRSTAT3 0x5000C010 UART 3 Tx/Rx status UERSTAT3 0x5000C014 UART 3 Rx error status UFSTAT3 0x5000C018 UART 3 FIFO status UTXH3 0x5000C020 UART 3 transmission hold...
Page 55 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write EP0CR 0x4980_0028 EP0 Control Register SCR2 0x4980_005C 0x1F System Control Register2 EP0BR 0x4980_0060 EP0 Buffer Register EP1BR 0x4980_0064 EP1 Buffer Register EP2BR 0x4980_0068 EP2 Buffer Register...
Page 56 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write IICDS0 0x5400000C IIC0 data shift IICLC0 0x54000010 IIC0 multi-master line control IICCON1 0x54000100 IIC1 control IICSTAT1 0x54000104 IIC1 status IICADD1 0x54000108 IIC1 address IICDS1 0x5400010C...
Page 57 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write GPEDAT 0x56000044 Port E data GPEUDP 0x56000048 0x55555555 Pull-up/down control E GPESEL 0x5600004c Selects the function of port E GPFCON 0x56000050 Port F control GPFDAT...
Page 58 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write GSTATUS1 0x560000b0 0x32440001 Chip ID DSC0 0x560000c0 0x2AAAAAAA Strength control register 0 DSC1 0x560000c4 0xAAAAAAA Strength control register 1 DSC2 0x560000c8 0xAAAAAAA Strength control register 2...
Page 59 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write CH_CFG 0x52000000 0x40 SPI configuration register Clk_CFG 0x52000004 Clock configuration register MODE_CFG 0x52000008 SPI FIFO control register Slave_slection_reg 0x5200000C Slave selection signal SPI_INT_EN 0x52000010 SPI Interrupt Enable register...
Page 60 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write RSPREG2 0x4AC00018 0x00000000 Response Register 2 RSPREG3 0x4AC0001C 0x00000000 Response Register 3 BDATA 0x4AC00020 Not fixed Buffer Data Register PRNSTS 0x4AC00024 0x00000000 Present State Register...
Page 61 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write BLKSIZE 0x4A800004 0x00000000 Host DMA Buffer Boundary and Transfer Block Size Register BLKCNT 0x4A800006 0x00000000 Blocks Count For Current Transfer ARGUMENT 0x4A800008 0x00000000 Command Argument Register...
Page 62 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write CONTROL2 0x4A800080 0x00000000 Control register 2 CONTROL3 0x4A800084 0x7F5F3F1F FIFO Interrupt Control (Control Register 3) DEBUG 0x4A800088 Not fixed Debug register CONTROL4 0x4A80008C 0x00000000 HCVER...
Page 63 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write INTEN_REG 0x4D408004 0x0000_0000 Interrupt Enable register. FIFO_INTC_REG 0x4D408008 0x0000_0018 Interrupt Control register. INTC_PEND_REG 0x4D40800C 0x0000_0000 Interrupt Control Pending register. FIFO_STAT_REG 0x4D408010 0x0000_0600 Command FIFO Status reg...
Page 64 PRODUCT OVERVIEW S3C2451X RISC MICROPROCESSOR Acc. Read/ Register Name Address Reset Value Function Unit Write COORD0_X_REG 0x4D408304 0x0000_0000 X coordinate of Coordinates 0. COORD0_Y_REG 0x4D408308 0x0000_0000 Y coordinate of Coordinates 0. COORD1_REG 0x4D408310 0x0000_0000 Coordinates 1 register. COORD1_X_REG 0x4D408314 0x0000_0000 X coordinate of Coordinates 1.
Page 65 S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW Acc. Read/ Register Name Address Reset Value Function Unit Write SRC_BASE_ADDR_ 0x4D408730 0x0000_0000 Source Image Base Address register DEST_BASE_ADDR 0x4D408734 0x0000_0000 Dest Image Base Address register _REG (in most cases, frame buffer address) Preliminary product information describe products that are in development, 1-61 for which full characterization data and associated errata are not yet available.
Page 66 S3C2451X RISC MICROPROCESSOR Cautions on S3C2451X Special Registers 1. S3C2451X does not support the big endian mode. 2. The special registers have to be accessed for each recommended access unit. 3. All registers except ADC registers, RTC registers and UART registers must be read/write in word unit (32-bit).
Page 67 533MHz, while the AHB blocks and the APB blocks operate on 133MHz and 66MHz, respectively. Thus, the power control of the ARM core is major issue to reduce the overall power dissipation in S3C2451X, and IDLE mode is supported for this purpose. In IDLE mode, the ARM core is not operated until the external interrupts or internal interrupts.
Page 68 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR BLOCK DIAGRAM off-part alive-part Glue Glue Reset Reset Clock Control Clocks Power Generator ON/OFF Power Management Signal Power Management Masking Register Register Figure 2-1. System controller block diagram Figure 2-1 shows the system controller block diagram. The system controller is divided into two blocks, which are the OFF block and the ON block.
Page 69 In this section, the behavior will be described. RESET MANAGEMENT AND TYPES S3C2451x has four types of resets and reset controller in system controller can place the system into the predefined states with one of the following four resets.
Page 70 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR POWER nRESET EXTCLK or XTIpll PLL is configured by S/W first time Clock Lock time disable VCO is adapte to new clock frequency output SYSCLK The logic is operarted by SYSCLK is FOUT EXTCLK or XTIpll Figure 2-2.
Page 71 7. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted. WAKEUP RESET When S3C2451X is woken up from SLEEP mode by wakeup event, the wakeup reset is invoked. The detail description will be explained in the power management mode section.
Page 72 CLOCK SOURCE SELECTION Table 2-2 and 2-3 show the relationship between the combination of mode control pins OM[0] and the selection of source clock for S3C2451X. Table 2-2. Clock source selection for the main PLL and clock generation logic MPLL Reference Clock...
Page 73 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER Table 2-3. Clock source selection for the EPLL CLKSRC[7] (register) CLKSRC[8] (register) OM[0] EPLL Reference Clock EXTCLK EXTCLK Table 2-4. PLL & Clock Generator condition MPLLCAP : N/A Loop filter capacitance EPLLCAP :Typical 1.8nF 5% MPLL: 10 –...
Page 74 CHANGE PLL SETTINGS IN NORMAL OPERATION During the operation of S3C2451X in NORMAL mode, if the user wants to change the frequency by writing the PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the internal blocks in S3C2451X.
Page 75 SYSTEM CONTROLLER SYSTEM CLOCK CONTROL The ARMCLK is used for ARM926EJ core, the main CPU of S3C2451X. The HCLK is the reference clock for internal AHB bus and peripherals such as the memory controller, the interrupt controller, LCD controller, the DMA, USB host block, System Controller, Power down controller and etc.
Page 76 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR ARM & BUS CLOCK DIVIDE RATIO The MSysClk is the base clock for S3C2451 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc. The table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register.
Page 77 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER EXAMPLES FOR CONFIGURING CLOCK REGITER TO PRODUCE SPECIFIC FREQUENCY OF AMBA CLOCKS. When PLL output frequency = 533MHz Target frqeuency ARMCLK = 533MHz, HCLK = 133MHz, PCLK = 66MHz, DDRCLK = 266MHz SSMCCLK = 66MHz Register value ARMDIV = 4’b0000,...
Page 78 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR Figure 2-9 shows EPLL and special clocks for various peripherals Figure 2-9. EPLL Based clock domain ESYSCLK CONTROL Clocks of the EPLL can be used for various peripherals. Each divider value is configured in CLKDIV1 register and all clocks are enabled or disabled by accessing SCLKCON register.
Page 79 The power management block controls the system clocks by software for the reduction of power consumption in S3C2451X. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal. S3C2451X has four power-down modes. The following section describes each power management mode.
Page 80 PLL locking-time is required to provide stabilized ARMCLK. Those time-waits are automatically inserted by the hardware of S3C2451X. During these time-waits, the clock is not supplied to the internal logic circuitry. STOP mode Entering sequence is as follows Set the STOP Mode bit ( by the main CPU) System controller requests bus controller to finish bus transactions of ARM Core.
Page 81 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER STOP mode Exiting sequence is as follows 1. Enable X-tal Oscillator if it is used, and wait the OSC settle down (around 1ms). 2. After the Oscillator settle-down, the System Clock is fed using the PLL input clock and also enable the PLLs and waits the PLL locking time 3.
Page 82 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR Figure 2-11. Entering STOP mode and exiting STOP mode (wake-up) Preliminary product information describe products that are in development, 2-16 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 83 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER SLEEP mode is initiated Wake-up event ARM Down Req. & Ack. ARMCLK BUS Down Req. & Ack. DRAM Self Refresh Req. & Ack. CKE (DRAM) SYSCLK PWR_EN Figure 2-12. Entering SLEEP mode and exiting SLEEP mode (wake-up)
Page 84 S3C2451X RISC MICROPROCESSOR WAKE-UP EVENT When S3C2451X wakes up from the STOP Mode by an External Interrupt, a RTC alarm interrupt and other interrupts, the PLL is turned on automatically. The initial-state of S3C2451X after wake-up from the SLEEP Mode is almost the same as the Power-On-Reset state except for the contents of the external DRAM is preserved.
Page 85 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER POWER SAVING MODE ENTERING/EXITING CONDITION Table 2-8 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering conditions are set by the main CPU. Pleas refer to power-related registers(PWRMODE, PWRCFG and WKUPSTAT) before apopting power saving scheme on your system.
Page 86 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR REGISTER DESCRIPTIONS The system controller registers are divided into seven categories; clock source control, clock control, power management, reset control, system controller status, bus configuration, and misc. The following section will describe the behavior of the system controller.
Page 87 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER INDIVIDUAL REGISTER DESCRIPTIONS CLOCK SOURCE CONTROL REGISTERS (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, AND EPLLCON) The six registers control two internal PLLs and an external oscillator. The output frequency of the PLL is determined by the divider values of MPLLCON and EPLLCON. The stabilization time for PLLs and the oscillator is controlled by LOCKCON0/1 and OSCSET, respectively.
Page 88 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR MPLLCON Description Initial Value 0x00 RESERVED [31:26] MPLLEN_STOP [25] MPLL ON/OFF in STOP mode. 0:OFF, 1:ON ONOFF [24] MPLL ON/OFF. 0:ON, 1:OFF MDIV [23:14] Main divider value of MPLL 0x215 RESERVED [13:11] PDIV [10:5] Pre-divider value of MPLL...
Page 89 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER EPLLCON Description Initial Value RESERVED [31:26] 0x00 EPLLEN_STOP [25] EPLL ON/OFF in STOP mode. 0:OFF, 1:ON ONOFF [24] EPLL ON/OFF. 0:ON, 1:OFF MDIV [23:16] EPLL main divider value 0x20 RESERVED [15:14] PDIV [13:8] EPLL pre-divider value...
Page 90 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR CLOCK CONTROL REGISTER (CLKSRC, CLKDIV, HCLKCON, PCLKCON, AND SCLKCON) The clock generator within the system controller has many dividers and MUXs to generate appropriate clocks. These clocks are controlled by the clock control registers as described in here.
Page 91 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER The CLKSRC selects the source input of the clocks. CLKSRC Description Initial Value 0x0_0000 RESERVED [31:21] Source clock of CAMCLK divider SEL_CAMCLK [20] 0 = EPLL, 1 = HCLK HS-SPI0 clock SELHSSPI1 [19] 0 = EPLL (divided), 1 = MPLL (divided)
Page 92 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR The CLKDIV0 configures the division ratio of each clock generator. The operating speed of ARM can be slow to reduce the overall power dissipation, if software doest not require full operating performance. In this case, the power dissipation due to the ARM core can be reduced if the DVS field is ON.
Page 93 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER CLKDIV1 configures the clock ratio related on EPLL. CLKDIV1 Description Initial Value RESERVED [31:30] CAM clock divider ratio. CAMDIV [29:26] ratio = CAMDIV + 1 SPIDIV_0 [25:24] HS-SPI clock divider ratio, ratio = (SPIDIV +1)
Page 94 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR The AHB and APB clocks are en/disabled by HCLKCON register. All reserved bits have 1 value at initial state. HCLKCON Description Initial Value RESERVED [31:21] 0x7FF [20] Enable HCLK into 2D DRAMC [19] Enable HCLK into DRAM controller...
Page 95 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER The special clocks are controlled by SCLKCON register. Some blocks in the device require several operating frequencies, i.e., 48 MHz and 24 MHz for USB interface block. Thus, these output frequencies can be controlled by the CLKDIV values.
Page 96 Power management configuration register 0x0000_0000 S3C2451X consists of three power-down modes, which are IDLE, STOP, and SLEEP. The mode transition from the NORMAL mode occurs when the appropriate value is written into PWRMODE register. If software tries to write illegal value, i.e., tries to set multiple power modes concurrently, then the write operation will be ignored.
Page 97 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER PWRCFG register controls the configuration of power mode transition. PWRCFG Description Initial Value RESERVED [31:17] 0x0000 Enable the system enters DEEP-STOP mode. If user set 16th registerof PWRMODE reg. (ie. STOP) while this bit is configured to ‘1’, the system enters DEEP-STOP...
Page 98 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR RESET CONTROL REGISTERS (SWRST AND RSTCON) Software can reset S3C2451X using SWRST register. The waveform of the reset signals are determined by RSTCON register. Register Address Description Reset Value SWRST 0x4C00_0044 Software reset control register...
Page 99 Figure 2-13. Usage of PWROFF_SLP S3C2451X has a lot of retention PADs. Retention pad’s ability is remaining data when internal logic power is off. In normal mode, PWROFF_SLP signal which from RSTCON register can cotrol about PAD output. If SLP_IN signal has LOW value, data assigned to specific PAD go out through level shifter and latch.
Page 100 0x0000_0000 After S3C2451X is re-set or woken-up, the following two registers store the source of the activation. The value of RSTSTAT register is cleared by the other reset. If each bit has ‘1’ value, resets or wakeup events are occurred.
Page 101 Bus priority control register 0 0x0000_0000 S3C2451x consists of 2 hierarchical AHB buses. The arbitration priority and order can be configured with BUSPRI0 registers. You can see specific priority number that assigned to each AMBA master in User’s Manual section ‘04-BUS PRIORITIES’. The number of masters of AHB-S and AHB-I bus is 16 and 9 respectively.
Page 102 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR Initial BUSPRI0 Description Value TYPE_I [7:6] Priority type for AHB-Image bus RESERVED [5:3] Fixed priority order for AHB-I bus Value Priority Value Priority 3’b000 0-1-2-3-4-5-6-7 3’b100 4-5-6-0-1-2-3-7 ORDER_I [2:0] 3’b001 1-2-3-4-5-6-0-7 3’b101 5-6-0-1-2-3-4-7 3’b010 2-3-4-5-6-0-1-7 3’b110...
Page 103 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER USB PHY CONTROL REGISTER (PHYCTRL) Register Address Description Reset Value PHYCTRL 0x4C00_0080 USB2.0 PHY Control Register 0x0000_0000 PHYCTRL Description Initial State RESERVED [31:5] CLK_SEL [4:3] Reference Clock Frequency Select 2’b00 00 = 48MHz 01 = Reserved...
Page 104 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR USB PHY POWER CONTROL REGISTER (PHYPWR) Register Address Description Reset Value PHYPWR 0x4C00_0084 USB2.0 PHY Power Control Register 0x0000_0000 PHYCTRL Description Initial State COMMON_ON_N [31] Force XO(Crystal Oscillator), Bias, Bandgap, and PLL to Remain Powered During a Suspend This signal controls the power-down signals of sub-blocks in the Common block when the USB 2.0 PHY is suspended.
Page 105 S3C2451X RISC MICROPROCESSOR SYSTEM CONTROLLER USB RESET CONTROL REGISTER (URSTCON) Register Address Description Reset Value URSTCON 0x4C00_0088 USB Reset Control Register 0x0000_0000 URSTCON Description Initial State RESERVED [31:3] FUNC_RESET Function 2.0 S/W Reset 1: reset HOST_RESET Host 1.1 S/W Reset...
Page 106 SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, 2-40 for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 107 S3C2451X RISC MICROPROCESSOR BUS MATRIX & EBI BUS MATRIX & EBI OVERVIEW S3C2451 MATRIX provides the interface between dual AHB bus and Memory sub-system. It is used for achieving high system performance by accessing various kinds of memory (SDRAM, SRAM, Flash Memory, ROM etc) from different AHB bus (one is for system and the other is for image) at the same time.
Page 108 BUS MATRIX & EBI S3C2451X RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS MATRIX CORE 0 PRIORITY REGISTER (BPRIORITY0) Register Address Description Reset Value BPRIORITY0 0X4E800000 Matrix Core 0 priority control register 0x0000_0004 BPRIORITY0 Description Initial State PRI_TYP Priority type 0: Fixed Type...
Page 109 S3C2451X RISC MICROPROCESSOR BUS MATRIX & EBI EBI CONTROL REGISTER (EBICON) Register Address Description Reset Value EBICON 0X4E800008 EBI control register 0x0000_0004 EBICON Description Initial State BANK3_CFG [10] Bank3 Configuration 0: SROM 1:CF BANK2_CFG Bank2 Configuration 0: SROM 1:CF BANK1_CFG...
Page 110 BUS MATRIX & EBI S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 111 S3C2451X RISC MICROPROCESSOR BUS PRIORITIES BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. BUS PRIORITY MAP The S3C2451 holds 16 masters on the AHB_S(System Bus), 9 masters on the AHB_I(Image Bus) and 9masters on the APB Bus.
Page 112 BUS PRIORITIES S3C2451X RISC MICROPROCESSOR Priority AHB_I BUS MASTERS Comment Reserved 1. Fix Type: all priority can be changed according to register value stored in The System Controller. TFTW1-LCD TFTW2-LCD 2 Rotation Type : all masters’ priority can be rotatable according to CAMIF_PREVIEW register value stored in The System Controller.
Page 113 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER STATIC MEMORY CONTROLLER (SMC) OVERVIEW The SMC provides simultaneous support for up to six memory banks (bank0 to bank5) that you can configure independently. Each memory bank supports: • SRAM • • Flash EPROM •...
Page 114 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR FEATURE • Supports asynchronous static memory-mapped devices including RAM, ROM, OneNAND and flash • Supports synchronous static memory-mapped devices including synchronous burst flash • Supports asynchronous page mode read operation in non-clocked memory subsystems •...
Page 115 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BLOCK DIAGRAM SMC Core Memory Control Signals AHB Slave Interface Interface AHB Slave Interface Data and Address Bus Data bus Interface Figure 5-1. SMC Block Diagram nWAIT Synchronizer Module SMCANCELWAIT AHB Slave AHB I/F...
Page 116 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR ASYNCHRONOUS READ Figure 5-3 shows an external memory read transfer with two output enable delay states, WSTOEN = 2, and two wait states, WSTRD = 2. Four AHB wait states are inserted during the transfer, two for the standard read, and additional two because of the programmed wait states added.
Page 117 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SMCLK ADDR nWAIT DATA ( R ) D(A) Figure 5-5. Read Timing Diagram (DRnCS = 1, DRnOWE = 1) Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 118 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR ASYNCHRONOUS BURST READ The SMC supports sequential access asynchronous burst reads to four or eight consecutive locations in 8 or 16- bit memories, as set using the BurstLenRead bits of the Control Register SMBCRx. Burst mode is enabled by setting the Burst Mode bits, BMRead or BMWrite, in the Control register.
Page 119 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SYNCHRONOUS READ/SYNCHRONOUS BURST READ Single synchronous read operations have the same control signal timing as an asynchronous read operation, but with different timing requirements for setup and hold relative to the clock. Because the output signals of the SMC are generated internally from clocked logic, the timing for single synchronous reads is the same as for asynchronous reads.
Page 120 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR ASYNCHRONOUS WRITE You can program the delay between the assertion of the chip select and the write enable from 0-15 cycles using the WSTWEN bits of the Bank Write Enable Assertion Delay Control Register, SMBWSTWENRx. This reduces the power consumption for memories.
Page 121 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SMCLK ADDR nWAIT DATA ( W ) D ( A ) Figure 5-9. Write Timing Diagram (DRnCS = 1, DRnOWE = 0) SMCLK ADDR nWAIT DATA ( W ) D ( A ) Figure 5-10. Write Timing Diagram (DRnCS = 1, DRnOWE = 1) Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 122 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR SYNCHRONOUS WRITE/ SYNCHRONOUS BURST WRITE Figure 5-11 shows an example synchronous write operation. In this example the signal SMADDRVALID provides a one-cycle pulse. This behavior is enabled by setting the SyncWriteDev bit in the SMBCRx register. You must also set the AddrValidWriteEn bit for synchronous write.
Page 123 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BUS TURNAROUND You can configure the SMC for each memory bank to use external bus turnaround cycles between read and write memory accesses. You can program the IDCY field for up to 15 bus turnaround wait states. This avoids bus contention on the external memory data bus.
Page 124 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR Scenario Examples ADDR<->CS: 3-cycle, CS<->OE: 4-cycle, CS<->WE: 5-cycle Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 5-12 Specifications and information herein are subject to change without notice.
Page 125 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SRAM Memory Interface Examples Figure 5-13. Memory Interface with 8-bit SRAM (2MB) Figure 5-14. Memory Interface with 16-bit SRAM (4MB) SRAM/ROM S3C2451 Addr. connection 8bit data bus RADDR0 16bit data bus RADDR0 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 126 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR SPECIAL REGISTERS BANK IDLE CYCLE CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBIDCYR0 0x4F000000 Bank0 idle cycle control register SMBIDCYR1 0x4F000020 Bank1 idle cycle control register SMBIDCYR2 0x4F000040 Bank2 idle cycle control register...
Page 127 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BANK WRITE WAIT STATE CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBWSTWRR0 0x4F000008 Bank0 write wait state control register 0x1F SMBWSTWRR1 0x4F000028 Bank1 write wait state control register 0x1F SMBWSTWRR2 0x4F000048 Bank2 write wait state control register...
Page 128 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR BANK WRITE ENABLE ASSERTION DELAY CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBWSTWENR0 0x4F000010 Bank0 write enable assertion delay control register SMBWSTWENR1 0x4F000030 Bank1 write enable assertion delay control register SMBWSTWENR2 0x4F000050 Bank2 write enable assertion delay control register...
Page 129 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BANK CONTROL REGISTERS 0-5 Register Address Description Reset Value SMBCR0 0x4F000014 Bank0 control register See note in p5-17 SMBCR1 0x4F000034 Bank1 control register 0x303000 SMBCR2 0x4F000054 Bank2 control register 0x303010 SMBCR3 0x4F000074 Bank3 control register...
Page 130 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR Description Initial State SyncReadDev Synchronous access capable device connected. Access the device using synchronous accesses for reads: 0: Asynchronous device (default). 1: Synchronous device. BMRead Burst mode read and asynchronous page mode: 0: Nonburst reads from memory devices (default at reset).
Page 131 S3C2451X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER BANK ONENAND TYPE SELECTION REGISTER Register Address Description Reset Value SMBONETYPER 0x4F000100 SMC Bank OneNAND TYPE SELECTION REGISTER Description Initial State [31:6] Read undefined. BANK5TYPE 0: DEMUXED OneNAND 1: MUXED OneNAND BANK4TYPE 0: DEMUXED OneNAND...
Page 132 STATIC MEMORY CONTROLLER S3C2451X RISC MICROPROCESSOR SMC CONTROL REGISTER Register Address Description Reset Value SMCCR 0x4F000204 SMC control register Description Initial State [31:2] Read undefined. Write as zero. MemClkRatio Defines the ratio of SMCLK to HCLK: 0: SMCLK = HCLK.
Page 133 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER MOBILE DRAM CONTROLLER OVERVIEW The S3C2451 Mobile DRAM Controller supports three kinds of memory interface - (Mobile) SDRAM and mobile DDR and DDR2. Mobile DRAM controller provides 2 chip select signals (2 memory banks), these are used for up to 2 (mobile) SDRAM banks or 2 mobile DDR banks or 2 DDR2 banks.
Page 134 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR Block Diagram • Follow figure 6-1 shows the block diagram of Mobile DRAM Controller Figure 6-1. Mobile DRAM Controller Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 135 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER MOBILE DRAM INITIALIZATION SEQUENCE On power-on reset, software must initialize the memory controller and the mobile DRAM connected to the controller. Refer to the mobile DRAM(SDRAM or mDDR or DDR2) data sheet for the start up procedure, and...
Page 136 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR 8. Issue a PALL(pre-charge all) command. Program the INIT[1:0] to ‘01b’. This automatically issues a PALL(pre-charge all) cammand to the DRAM. 9. Issue 2 or more auto-refresh commands. 10. Issue a MRS command with LOW to A8 to initialize device operation.
Page 137 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER (Mobile) SDRAM Memory Interface Examples DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 LDQM DQM1 UDQM nSCS nSCS0 SCKE SCKE nSRAS nSRASn SCLK SCLK nSCAS SCASn Figure 1 Memory Interface with 16-bit SDRAM (4Mx16, 4banks)
Page 138 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR Mobile DDR (and DDR2) Memory Interface Examples DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 LDQM DQM1 UDQM nSCS nSCS0 DQS0 DQS0 nSRAS nSRASn DQS1 DQS1 nSCAS SCASn SCKE SCLK SCLKn Figure 6-2. Memory Interface with 16-bit Mobile DDR and DDR2 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 139 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER Supported programmable timing parameters Figure 6-3 DRAM Timing diagram Figure 6-3 shows a timing diagram of DRAM. There are many timing parameters provided by DRAM. And DRAMC only provides some timing parameters to support various DRAM memories, like SDR, mobile DDR and DDR2.
Page 140 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR Figure 6-5 tARFC timing diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 141 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER Moble DRAM Configuration Register Register Address Description Reset Value BANKCFG 0x48000000 Mobile DRAM configuration register 0x0000_000C BANKCFG Description Initial State Reserved [31:19] Reserved 0x0000 The bit width of RAS (row) address of bank 0...
Page 142 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROL REGISTER Register Address Description Reset Value BANKCON1 0x48000004 Mobile DRAM control register 0x4400_0040 BANKCON Description Initial State DRAM controller status bit (read only) BUSY [31] 0 = IDLE 1 = BUSY...
Page 143 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER MOBILE DRAM TIMMING CONTROL REGISTER Register Address Description Reset Value BANKCON2 0x48000008 Mobile DRAM timing control register 0x0099_003F TIMECON Description Initial State Reserved [31:24] Reserved 0x00 Row active time 0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4-clock...
Page 144 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR MOBILE DRAM (EXTENDED ) MODE REGISTER SET REGISTER Register Address Description Reset Value BANKCON3 0x4800000C Mobile DRAM (E)MRS Register 0x8000_0003 1) mSDRAM / mDDR PnBANKCON Description Initial State [31:30] Bank address for EMRS Reserved [29:23] Should be ‘0’...
Page 145 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 2) DDR2 memory MRS[15:0] and EMRS(1)[31:16] PnBANKCON Description Initial State [31:30] Bank address for EMRS Reserved [29] Should be ‘0’ Qoff [28] 0 = Output buffer enable 1 = Output buffer disable RDQS [27]...
Page 146 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR 3) DDR2 memory EMRS(2)[31:16] PnBANKCON Description Initial State [31:30] Bank address for EMRS Reserved [29:24] Should be ‘0’ 000000b High Temperature Self-Refresh Rate Enable [23] 0 = Disable 1 = Enable Reserved [22:20] Should be ‘0’...
Page 147 S3C2451X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER Mobile DRAM Refresh CONTROL REGISTER Register Address Description Reset Value REFRESH 0x48000010 Mobile DRAM refresh control register 0x0000_0020 REFRESH Description Initial State Reserved [31:16] Reserved 0x0000 DRAM refresh cycle. Example: Refresh period is 15.6us, and HCLK is 66MHz. The...
Page 148 MOBILE DRAM CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 6-16 Specifications and information herein are subject to change without notice.
Page 149 NAND FLASH CONTROLLER 7.1 OVERVIEW S3C2451X boot code can be executed on an external NAND flash memory. The S3C2451X is equipped with an internal SRAM buffer called ‘Steppingstone’. This supports NAND flash boot loader. When you use IROM boot and select nand flash as boot device, first 8 KB of the NAND flash memory will be loaded in the Steppingstone by IROM and the boot code will be executed in the steppingstone.
Page 150 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.3 BLOCK DIAGRAM nFCE ECC Gen. NAND FLASH Interface Control & State Machine I/O0 - I/O7 Slave I/F Stepping Stone Stepping Stone Controller (64KB SRAM) Figure 7-1. NAND Flash Controller Block Diagram 7.4 BOOT LOADER FUNCTION...
Page 151 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.5 GPC5/6/7 PIN CONFIGURATION TABLE IN IROM BOOT MODE Page Address Cycle GPC7 [2] GPC6 [1] GPC5 [0] MMC(MoviNAND/iNand) Reserved Nand 2048 4096 Above configuration is applicable when NAND Flash is used as booting memory in IROM boot mode. If NAND Flash is not used as boot memory, the configuration can be changed by setting NFCON SFR ’NFCONF’...
Page 152 Figure 7-4. nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram 7.7 NAND FLASH ACCESS S3C2451X does not support NAND flash access mechanism directly. It only supports signal control mechanism for NAND flash access. Therefore software is responsible for accessing NAND flash memory correctly.
Page 153 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER C. Byte Access Register Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0] NFDATA Invalid value Invalid value Invalid value I/O[ 7:0] 7.9 STEPPINGSTONE (8KB IN 64KB SRAM) The NAND Flash controller uses Steppingstone as the buffer on booting and also you can use this area for various other purpose.
Page 154 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.10.2 1-BIT ECC PROGRAMMING ENCODING AND DECODING 1. To use 1-bit ECC in software mode, reset the ECCType to ‘0’ (enable 1-bit ECC)‘. ECC module generates ECC parity code for all read / write data when MainECCLock (NFCONT[7]) and SpareECCLock (NFCONT[6]) are unlocked(‘0’).
Page 155 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.10.4 4-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 4-bit ECC, set the MsgLength to 0(512-byte message length) and set the ECCType to ‘1’(enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. So, you have to reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’...
Page 156 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR The parity codes have self-correctable information include parity code itself. 4. To generate spare area ECC parity code, set the MsgLength to 1(24-byte message length), and set the ECCType to “01”(enable 8bit ECC). 8bit ECC module generates the ECC parity code for 24-byte data. In order to initiating the module, you have to write ‘1’...
Page 157 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER cycles to find any error. During this time, you can continue reading main data from external NAND flash memory. ECCDecDone(NFSTAT[6]) can be used to check whether ECC decoding is completed or not. When ECCDecDone (NFSTAT[6]) is set (‘1’), NF8ECCERR0 indicates whether error bit exist or not. If any error exists, you can fix it by referencing NF8ECCERR0/1/2 and NF8MLCBITPT register.
Page 158 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.11 Memory mapping(NAND boot and Other boot) SRAM SRAM (8KB) (8KB) 0x40000_0000 SDRAM SDRAM (nSCS1) (nSCS1) MPORT1 0x3800_0000 SDRAM SDRAM (nSCS0) (nSCS0) 0x3000_0000 SROM SROM (nRCS5) (nRCS5) 0x2800_0000 SROM SROM (nRCS4) (nRCS4) 0x2000_0000 SROM...
Page 159 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.12 NAND FLASH MEMORY CONFIGURATION Figure 7-6. A 8-bit NAND Flash Memory Interface Block Diagram NOTE: NAND CONTROLLER can support to control two nand flash memories . NAND CS Other BOOT nFCE NAND CONTROLLER CS0...
Page 160 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.13 NAND FLASH CONTROLLER SPECIAL REGISTERS 7.13.1 NAND FLASH CONTROLLER REGISTER MAP Address Reset value Name Description Base + 0x00 0xX000_100X NFCONF Configuration register Base + 0x04 0x0001_00C6 NFCONT Control register Base + 0x08...
Page 161 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.2 NAND FLASH CONFIGURATION REGISTER Register Address Description Reset Value NFCONF 0x4E000000 NAND Flash Configuration register 0xX000100X NFCONF Description Initial State Reserved [31] Reserved Reserved [30] Should be 0 Reserved [29:26] 0000 Reserved MsgLength...
Page 162 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR This bit can be changed by software later. AddrCycle H/W Set This bit indicates the number of Address cycle of NAND Flash memory. (CfgAddrCycle) When Page Size is 512 Bytes, 0: 3 address cycle...
Page 163 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.3 CONTROL REGISTER Register Address Description Reset Value NFCONT 0x4E000004 NAND Flash control register 0x000100C6 NFCONT Description Initial State Reserved [31:19] Reserved ECC Direction [18] 4-bit, 8-bitECC encoding / decoding control 0: Decoding 4-bit, 8bit ECC, It is used for page read...
Page 164 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR NFCONT Description Initial State EnbIllegalAccINT [10] Illegal access interrupt control 0: Disable interrupt 1: Enable interrupt Illegal access interrupt will occurs when CPU tries to program or erase locking area (the area setting in NFSBLK (0x4E000020) to NFEBLK (0x4E000024)).
Page 165 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.4 COMMAND REGISTER Register Address Description Reset Value NFCMMD 0x4E000008 R/W NAND Flash command set register 0x00 NFCMMD Description Initial State Reserved [31:8] Reserved 0x00 NFCMMD [7:0] NAND Flash memory command value 0x00 7.13.5 ADDRESS REGISTER...
Page 166 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.13.7 MAIN DATA AREA ECC REGISTER Register Address Description Reset Value NFMECCD0 0x4E000014 R/W NAND Flash ECC 1 register for main area data read 0x00000000 (Note) Refer to ECC MODULE FEATURES. NFMECCD1 0x4E000018 R/W NAND Flash ECC 3...
Page 167 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.9 PROGRMMABLE BLOCK ADDRESS REGISTER Register Address Description Reset Value NFSBLK 0x4E000020 R/W NAND Flash programmable start block address 0x000000 NFEBLK 0x4E000024 R/W NAND Flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address.
Page 168 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[16]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[17]) is set. NAND flash memory When NFSBLK > NFEBLK Address Locked area High (Read only)
Page 169 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.10 NFCON STATUS REGISTER Register Address Description Reset Value NFSTAT 0x4E000028 R/W NAND Flash operation status register 0x0080001D NFSTAT Description Initial State Reserved [31:24] Read undefined 0x00 Reserved [23:7] Reserved 0x00 ECCDecDone When 4-bit ECC or 8-bit ECC decoding is finished, this value set and issue interrupt if enabled.
Page 170 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.13.11 ECC0/1 ERROR STATUS REGISTER Register Address Description Reset Value NFECCERR 0x4E00002C NAND Flash ECC Error Status register for I/O [7:0] 0xX0XX_XXXX NFECCERR 0x4E000030 NAND Flash ECC Error Status register for I/O [7:0] 0x0000_0000 When ECCType is 1-bit ECC.
Page 171 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER When ECCType is 4-bit ECC. NFECCERR0 Description Initial State ECC Busy [31] Indicates the 4-bit ECC decoding engine is searching whether a error exists or not 0: Idle 1: Busy ECC Ready [30] ECC Ready bit...
Page 172 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.13.12 MAIN DATA AREA ECC0 STATUS REGISTER Register Address Description Reset Value NFMECC0 0x4E000034 NAND Flash ECC status register 0xXXXXXX NFMECC1 0x4E000038 NAND Flash ECC status register 0xXXXXXX When ECCType is 1-bit ECC NFMECC0...
Page 173 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.13 SPARE AREA ECC STATUS REGISTER Register Address Description Reset Value NFSECC 0x4E00003C NAND Flash ECC register for I/O [7:0] 0xXXXXXX NFSECC Description Initial State Reserved [31:16] Reserved 0xXXXX SECC0_1 [15:8] Spare area ECC1 Status for I/O[7:0]...
Page 174 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.13.15 ECC 0/1/2 FOR 8BIT ECC STATUS REGISTER Register Address Description Reset Value 0x4000_0000 NF8ECCERR0 0x4E00_0044 NAND Flash ECC Error Status register 0 0x0000_0000 NF8ECCERR1 0x4E00_0048 NAND Flash ECC Error Status register 1 0x0000_0000...
Page 175 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER MLCErrLocation8 [31:22] Error byte location of 8 bit error 0x000 Reserved [21] Reserved b’0 MLCErrLocation7 [20:11] Error byte location of 7 bit error 0x000 Reserved [10] Reserved b’0 MLCErrLocation6 [9:0] Error byte location of 6...
Page 176 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR 7.13.16 8BIT ECC MAIN DATA ECC 0/1/2/3 STATUS REGISTER Register Address Description Reset Value NFM8ECC0 0x4E00_0050 8bit ECC status register 0xXXXX_XXXX NFM8ECC1 0x4E00_0054 8bit ECC status register 0xXXXX_XXXX NFM8ECC2 0x4E00_0058 8bit ECC status register...
Page 177 S3C2451X RISC MICROPROCESSOR NAND FLASH CONTROLLER 7.13.17 8bit ECC ERROR PATTERN REGISTER Register Address Description Reset Value NFMLC8BITPT0 0x4E00_0060 R NAND Flash 8-bit ECC Error Pattern register0 for data[7:0] 0x0000_0000 NFMLC8BITPT1 0x4E00_0064 R NAND Flash 8-bit ECC Error Pattern register1 for data[7:0] 0x0000_0000...
Page 178 NAND FLASH CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 7-30 Specifications and information herein are subject to change without notice.
Page 179 S3C2451X RISC MICROPROCESSOR CF CONTROLLER CF CONTROLLER OVERVIEW CF controller supports PC card memory/IO mode & True-IDE mode. CF controller is compatible with CF standard spec. R3.0. FEATURES The CF controller features: The CF controller supports only 1 slot. The CF controller consists of 2 parts – PC card controller & ATA controller. They are multiplexing from or to PAD signals.
Page 180 CF CONTROLLER S3C2451X RISC MICROPROCESSOR SIGNAL DESCRIPTION CF interface Signals Pins Description nCD_CF Card detect signals (software control by GPIO MISCCR[30]) nIREQ_CF(EINT[19]) Interrupt request from CF card. PC card mode: active low (memory mode: level triggering, I/O mode: edge triggering). True-IDE mode: active high...
Page 181 S3C2451X RISC MICROPROCESSOR CF CONTROLLER BLOCK DIAGRAM Top-Level Block Diagram A top-level block diagram of the overall CF controller is shown below in Figure 8-1. CF controller AHB master IF ATA controller CF card AHB slave IF PC card controller...
Page 182 CF CONTROLLER S3C2451X RISC MICROPROCESSOR PC Card Controller Block Diagram A top-level block diagram of the PC card controller is shown below in Figure 8-2. PC card controller Block ADDR nWE,nOE Main nIOWR, nIORD Controller nREG AHB ADDR WDATA &...
Page 183 S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA Controller Block Diagram A top-level block diagram of the ATA controller is shown below in Figure 8-3. ATA controller Block PIO data AHB slave IF control/interrupt Slave interface ATA write data interface interface ATA read data...
Page 184 CF CONTROLLER S3C2451X RISC MICROPROCESSOR TIMING DIAGRAM PC Card Mode nCE1 nCE2 IORD IOWR IDLE SET UP COMMAND HOLD IDLE Figure 8-4. PC Card State Definition Area Attribute memory I/O interface Common memory (min, Max) nS Set up (30, --)
Page 185 S3C2451X RISC MICROPROCESSOR CF CONTROLLER True-IDE Mode PIO Mode PIO Mode Waveform CS0, CS1 DA[2:0] teoc DIOR-/ DIOW- DD[15:0] or DD[7:0] DD[15:0] or DD[7:0] Figure 8-5. PIO Mode Waveform Timing Parameter In PIO Mode Table 8-1. Timing Parameter Each PIO Mode...
Page 186 CF CONTROLLER S3C2451X RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS Memory Map Memory Map Diagram (HSEL_SLV_Base = 0x4B80_0000) SFR Area SFR_Base = HSEL_SLV_Base + 0 x 1800 Common Memory Area HSEL_SLV_Base + 0 x 1000 I/O Area HSEL_SLV_Base + 0 x 0800...
Page 187: Table Of Contents
S3C2451X RISC MICROPROCESSOR CF CONTROLLER Memory Map Table Table 8-2. Memory Map Table Register Address Description Reset Value SFR_BASE 0x4B801800 CF card host controller base address MUX_REG 0x4B801800 Top level control & configuration register 0x00000006 Reserved ~ 0x001C Reserved area...
Page 188 CF CONTROLLER S3C2451X RISC MICROPROCESSOR Table 8-3. Memory Map Table (Continued) Register Address Description Reset Value ATA_CADR_SBUF 0x4B801950 ATA current read address of source buffer 0x00000000 ATA_PIO_DTR 0x4B801954 ATA PIO device data register 0x00000000 ATA_PIO_FED 0x4B801958 ATA PIO device Feature/Error register...
Page 189 S3C2451X RISC MICROPROCESSOR CF CONTROLLER INDIVIDUAL REGISTER DESCRIPTIONS MUX_REG REGISTER Register Address Description Reset Value MUX_REG 0x4B801800 MUX_REG is used to set the internal mode, output 0x0000_0006 port enable & card power enable. MUX_REG Description Reset Value Reserved [31:3] Reserved bits...
Page 190: Pccard_Cfg
CF CONTROLLER S3C2451X RISC MICROPROCESSOR PCCARD CONFIGURATION & STATUS REGISTER Register Address Description Reset Value PCCARD_CFG 0x4B801820 PCCARD_CFG is used to set the configuration & 0x0000_0F0 read the status of card. PCCARD_CFG Bits Description Reset Value Reserved [31:14] Reserved bits...
Page 191: Pccard_Int
S3C2451X RISC MICROPROCESSOR CF CONTROLLER PCCARD INTERRUPT MASK & SOURCE REGISTER Register Address Description Reset Value PCCARD_INT 0x4B801824 PCCARD_INT is interrupt source & interrupt mask 0x0000_0600 register. PCCARD_INT Bits Description Reset Value Reserved [31:11] Reserved bits INTMSK_ [10] Interrupt mask bit of no card error...
Page 192 CF CONTROLLER S3C2451X RISC MICROPROCESSOR PCCARD_ATTR REGISTER Register Address Description Reset Value PCCARD_ 0x4B801828 PCCARD_ATTR is used to set the card access 0x0003_1909 ATTR timing. PCCARD_ATTR Bits Description Reset Value Reserved [31:23] Reserved bits HOLD_ATTR [22:16] Hold state timing of attribute memory area...
Page 193 S3C2451X RISC MICROPROCESSOR CF CONTROLLER PCCARD_COMM REGISTER Register Address Description Reset Value PCCARD_ 0x4B801830 PCCARD_COMM is used to set the card access 0x0003_1909 COMM timing. PCCARD_COMM Bits Description Reset Value Reserved [31:23] Reserved bits HOLD_COMM [22:16] Hold state timing of common memory area...
Page 194: Ata_Control
CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_CONTROL REGISTER Register Address Description Reset Value ATA_CONTROL 0x4B801900 ATA Control register 0x0000_0002 ATA_CONTROL Bits Description Reset Value Reserved [31:2] Reserved bits clk_down_ready Status for clock down This bit is asserted in idle state when ATA_CONTROL bit [0] is zero.
Page 195: Ata_Command
S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA_COMMAND REGISTER Register Address Description Reset Value ATA_COMMAND 0x4B801908 ATA Command register 0x0000_0000 ATA_COMMAND Bits Description Reset Value Reserved [31:2] Reserved bits xfr_command [1:0] ATA transfer command Four command types (START, STOP, ABORT and CONTINUE) are supported for data transfer control. The “START”...
Page 196 CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_SWRST REGISTER Register Address Description Reset Value ATA_SWRST 0x4B80190C ATA S/W RESET register 0x0000_0000 ATA_SWRST Bits Description Reset Value Reserved [31:1] Reserved bits ata_swrstn Software reset for the ATA host 0: No reset 1: Software reset for all ATA host module.
Page 197: Ata_Irq_Mask
S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA_IRQ_MASK REGISTER Register Address Description Reset Value ATA_IRQ_MASK 0x4B801914 ATA IRQ MASK register 0x0000_001F ATA_IRQ_MASK Bits Description Reset Value Reserved [31:5] Reserved bits mask_sbut_ Interrupt mask bit of source buffer empty empty_int 0 : unmask...
Page 198: Ata_Cfg
CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_CFG REGISTER Register Address Description Reset Value ATA_CFG 0x4B801918 ATA Configuration register 0x0000_0000 ATA_CFG Bits Description Reset Value Reserved [31:9] Reserved bits sbuf_empty_ Determines whether to continue automatically when mode source buffer is empty. This bit should not be changed during runtime operation.
Page 199 S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA_CFG Bits Description Reset Value byte_swap Determines whether data endian is little or big in 16bit data. 0 : little endian ( data[15:8], data[7:0] ) 1 : big endian ( data[7:0], data[15:8] ) atadev_irq_al Device interrupt signal level...
Page 200: Ata_Pio_Time
CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_PIO_TIME REGISTER Register Address Description Reset Value ATA_PIO_TIME 0x4B80192C ATA PIO Timing Control register 0x0001_C23 ATA_PIO_TIME Bits Description Reset Value Reserved [31:20] Reserved bits pio_teoc [19:12] PIO timing parameter, teoc, end of cycle time 0x1C It shall not have zero value.
Page 201 S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA_TBUF_START REGISTER Register Address Description Reset Value ATA_TBUF_ 0x4B80193C Start address of track buffer 0x0000_0000 START ATA_TBUF_ Bits Description Reset Value START track_buffer_ [31:2] Start address of track buffer (4byte unit) 0x00000000 start Reserved [1:0]...
Page 202 CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_SBUF_START REGISTER Register Address Description Reset Value ATA_SBUF_ 0x4B801944 Start address of source buffer 0x0000_0000 START ATA_SBUF_ Bits Description Reset Value START src_buffer_start [31:2] Start address of source buffer (4byte unit) 0x00000000 Reserved [1:0] Reserved bits...
Page 203 S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA_CADDR_TBUF REGISTER Register Address Description Reset Value ATA_CADDR_ 0x4B80194C Current address of track buffer 0x0000_0000 TBUF ATA_CADDR_ Bits Description Reset Value TBUF track_buf_ [31:2] Current address of track buffer 0x00000000 cur_adr Reserved [1:0] Reserved bits...
Page 204 CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_PIO_FED REGISTER Register Address Description Reset Value ATA_PIO_FED 0x4B801958 8bit PIO device feature/error register 0x0000_0000 ATA_PIO_FED Bits Description Reset Value Reserved [31:8] Reserved bits pio_dev_fed [7:0] 8-bit PIO device feature/error (command block) register 0x00 NOTE: pio_dev_fed can be read by accessing register ATA_PIO_RDATA...
Page 205 S3C2451X RISC MICROPROCESSOR CF CONTROLLER ATA_PIO_LMR REGISTER Register Address Description Reset Value ATA_PIO_LMR 0x4B801964 8-bit PIO device LBA middle register 0x0000_0000 ATA_PIO_LMR Bits Description Reset Value Reserved [31:8] Reserved bits pio_dev_lmr [7:0] 8-bit PIO device LBA middle (command block) register...
Page 206 CF CONTROLLER S3C2451X RISC MICROPROCESSOR ATA_PIO_CSD REGISTER Register Address Description Reset Value ATA_PIO_CSD 0x4B801970 8-bit PIO device command/status register 0x0000_0000 ATA_PIO_CSD Bits Description Reset Value Reserved [31:8] Reserved bits pio_dev_csd [7:0] 8-bit PIO device command/status (command block) 0x00 register NOTE: pio_dev_csd can be read by accessing register ATA_PIO_RDATA...
Page 207 S3C2451X RISC MICROPROCESSOR CF CONTROLLER BUS_FIFO_STATUS REGISTER Register Address Description Reset Value BUS_FIFO_ 0x4B801990 BUS FIFO status register 0x0000_0000 STATUS BUS_FIFO_ Bits Description Reset Value STATUS Reserved [31:19] Reserved bits bus_state[2:0] [18:16] 3’b000 : IDLE 0x00 Another value is in operation.
Page 208 CF CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 8-30 Specifications and information herein are subject to change without notice.
Page 209 DMA CONTROLLER OVERVIEW S3C2451X supports eight-channel DMA (Bridge DMA or peripheral DMA) controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. In other words, each channel can handle the...
Page 210 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR DMA REQUEST SOURCES Each channel of DMA controller can select one source among 27 DMA sources if H/W DMA request mode is selected by REQSEL register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) The 27 DMA sources for each channel are as follows.
Page 211 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER DMA OPERATION The details of DMA operation can be explained using three-state FSM (finite state machine) as follows: State-1. As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK and INT REQ are 0.
Page 212 Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation. The Figure. 9-1 shows the basic Timing in the DMA operation of the S3C2451X. • The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes.
Page 213 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER – Demand/Handshake Mode Comparison Related to the Protocol between XnXDREQ and XnXDACK These are two different modes related to the protocol between XnXDREQ and XnXDACK. Figure. 9-2 shows the differences between these two modes i.e., Demand and Handshake modes.
Page 214 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR Transfer Size • There are two different transfer sizes; single and Burst 4. • DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus.
Page 215 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER EXAMPLES OF POSSIBLE CASES Single service, Demand Mode, Single Transfer Size The assertion of XnXDREQ is need for every unit transfer (Single service mode), the operation continues while the XnXDREQ is asserted(Demand mode), and one pair of Read and Write(Single transfer size) is performed.
Page 216 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR DMA SPECIAL REGISTERS There are 10 control registers for each DMA channel. (Since there are six channels, the total number of control registers is 60.) Seven of them are to control the DMA transfer, and other three are to see the status of DMA controller.
Page 217 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER DMA INITIAL SOURCE CONTROL REGISTER (DISRCC) Register Address Description Reset Value DISRCC0 0x4B000004 DMA0 Initial Source Control Register 0x00000000 DISRCC1 0x4B000104 DMA1 Initial Source Control Register 0x00000000 DISRCC2 0x4B000204 DMA2 Initial Source Control Register 0x00000000...
Page 218 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR DMA INITIAL DESTINATION REGISTER (DIDST) Register Address Description Reset Value DIDST0 0x4B000008 DMA0 Initial Destination Register 0x00000000 DIDST1 0x4B000108 DMA1 Initial Destination Register 0x00000000 DIDST2 0x4B000208 DMA2 Initial Destination Register 0x00000000 DIDST3 0x4B000308 DMA3 Initial Destination Register...
Page 219 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER DMA INITIAL DESTINATION CONTROL REGISTER (DIDSTC) Register Address Description Reset Value DIDSTC0 0x4B00000C DMA0 Initial Destination Control Register 0x00000000 DIDSTC1 0x4B00010C DMA1 Initial Destination Control Register 0x00000000 DIDSTC2 0x4B00020C DMA2 Initial Destination Control Register 0x00000000...
Page 220 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR DMA CONTROL REGISTER (DCON) Register Address Description Reset Value DCON0 0x4B000010 DMA0 Control Register 0x00000000 DCON1 0x4B000110 DMA1 Control Register 0x00000000 DCON2 0x4B000210 DMA2 Control Register 0x00000000 DCON3 0x4B000310 DMA3 Control Register 0x00000000 DCON4 0x4B000410...
Page 221 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER DCONn Description Initial State SERVMODE [27] Select the service mode between single service mode and whole service mode. 0: single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request.
Page 222 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR DMA STATUS REGISTER (DSTAT) Register Address Description Reset Value DSTAT0 0x4B000014 DMA0 Count Register 000000h DSTAT1 0x4B000114 DMA1 Count Register 000000h DSTAT2 0x4B000214 DMA2 Count Register 000000h DSTAT3 0x4B000314 DMA3 Count Register 000000h DSTAT4 0x4B000414...
Page 223 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER DMA CURRENT SOURCE REGISTER (DCSRC) Register Address Description Reset Value DCSRC0 0x4B000018 DMA0 Current Source Register 0x00000000 DCSRC1 0x4B000118 DMA1 Current Source Register 0x00000000 DCSRC2 0x4B000218 DMA2 Current Source Register 0x00000000 DCSRC3 0x4B000318 DMA3 Current Source Register...
Page 224 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR DMA MASK TRIGGER REGISTER (DMASKTRIG) Register Address Description Reset Value DMASKTRIG0 0x4B000020 DMA0 Mask Trigger Register DMASKTRIG1 0x4B000120 DMA1 Mask Trigger Register DMASKTRIG2 0x4B000220 DMA2 Mask Trigger Register DMASKTRIG3 0x4B000320 DMA3 Mask Trigger Register DMASKTRIG4...
Page 225 S3C2451X RISC MICROPROCESSOR DMA CONTROLLER DMA REQUESET SELECTION register (DmaREQSEL) Register Address Description Reset Value DMAREQSEL0 0x4B000024 DMA0 Request Selection Register DMAREQSEL1 0x4B000124 DMA1 Request Selection Register DMAREQSEL2 0x4B000224 DMA2 Request Selection Register DMAREQSEL3 0x4B000324 DMA3 Request Selection Register DMAREQSEL4...
Page 226 DMA CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 9-18 Specifications and information herein are subject to change without notice.
Page 227 INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the S3C2451X receives the request from 59 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller.
Page 228 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR The interrupt controller has two groups of interrupt sources, and first group has always higher priority than the other group. Actually, we made this interrupt controller using by two interrupt controllers. The nRIQ of ARM926EJ is connected with ‘AND’...
Page 229 Interrupt Pending Register The S3C2451X has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure.
Page 230 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTERRUPT SOURCES The interrupt controller supports 51 interrupt sources as shown in the table below. Sources Descriptions Arbiter Group NONE Reserved ARB11 NONE Reserved ARB11 NONE Reserved ARB11 NONE Reserved ARB11 NONE Reserved ARB10 NONE...
Page 231 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER INT_SPI1 High speed SPI 1 interrupt ARB5 INT_UART0 UART0 Interrupt (ERR, RXD, and TXD) ARB5 INT_IIC0 IIC 0 interrupt ARB4 INT_USBH USB Host interrupt ARB4 INT_USBD USB Device interrupt ARB4 INT_NAND NAND Flash Controller interrupt...
Page 232 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 10-2 below. Figure 10-3. Priority Generating Block Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 233 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY We have two groups of arbiters. One group is ARBITER0~ARBITER5, and the other is ARMBITER6~ARBITER11. The former group has higher priority than the latter group. And priority of arbiters in each group can be set as below separately.
Page 234 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER SPECIAL REGISTERS There are following control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, interrupt pending register, interrupt offset register, sub-source pending register and sub-mask register.
Page 235 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER 0 = IRQ mode 1 = FIQ mode INTMSK2 0X4A000048 R/W Determine which interrupt source of group 2 is 0xFFFFFFFF masked. The masked interrupt source will not be serviced. 0 = Interrupt service is available.
Page 236 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR SOURCE PENDING (SRCPND 1) REGISTER FOR GROUP1(Continued) SRCPND 1 Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested INT_RTC [30] 0 = Not requested, 1 = Requested INT_SPI1 [29] 0 = Not requested,...
Page 237 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER SOURCE PENDING (SRCPND 2) REGISTER FOR GROUP2(CONTINUED) SRCPND 1 Description Initial State INT_I2S1 0 = Not requested, 1 = Requested INT_I2S0 0 = Not requested, 1 = Requested INT_PCM1 0 = Not requested, 1 = Requested...
Page 238 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt).
Page 239 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER nBATT_FLT 0 = IRQ, 1 = FIQ INT_CAM 0 = IRQ, 1 = FIQ EINT8_23 0 = IRQ, 1 = FIQ EINT4_7 0 = IRQ, 1 = FIQ EINT3 0 = IRQ, 1 = FIQ...
Page 240 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1).
Page 241 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER INT_WDT/AC97 0 = Service available, 1 = Masked INT_TICK 0 = Service available, 1 = Masked nBATT_FLT 0 = Service available, 1 = Masked INT_CAM 0 = Service available, 1 = Masked EINT8_23 0 = Service available,...
Page 242 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority. Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.
Page 243 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTPND1 Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested INT_RTC [30] 0 = Not requested, 1 = Requested INT_SPI1 [29] 0 = Not requested, 1 = Requested INT_UART0 [28] 0 = Not requested,...
Page 244 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTPND2 Description Initial State INT_I2S1 0 = Not requested, 1 = Requested INT_I2S0 0 = Not requested, 1 = Requested INT_PCM1 0 = Not requested, 1 = Requested INT_PCM0 0 = Not requested, 1 = Requested...
Page 245 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows, which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND. Register...
Page 246 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR Reserved INT_I2S1 Reserved INT_I2S0 Reserved INT_PCM1 Reserved INT_PCM0 Reserved Reserved Reserved Reserved Reserved INT_IIC1 Reserved INT_2D NOTE: FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt.
Page 247 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are.
Page 248 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR SUBSRCPND Description SRCPND Initial State Reserved [31] Not used SUBINT_DMA7 [30] 0 = Not requested, 1 = Requested INT_DMA SUBINT_DMA6 [29] 0 = Not requested, 1 = Requested SUBINT_AC97 [28] 0 = Not requested, 1 = Requested...
Page 249 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 27 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1).
Page 250 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR INTSUBMASK Description INTMASK Initial State Reserved [31] Not used SUBINT_DMA7 [30] 0 = Service available, 1 = Masked INT_DMA SUBINT_DMA6 [29] 0 = Service available, 1 = Masked SUBINT_AC97 [28] 0 = Service available, 1 = Masked...
Page 251 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY MODE REGISTER (PRIORITY_MODE) Register Address Description Reset Value PRIORITY_MODE 0x4A000030 IRQ priority mode register 0x00000000 PRIORITY_MODE 0x4A000070 IRQ priority mode register 0x00000000 PRIORITY_MODE1 Description Initial State ARB_MODE6 [27] Arbiter 6 group priority mode selection 0 = Fixed ends &...
Page 252 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR PRIORITY_MODE1 Description Initial State ARB_SEL3 [14:12] Arbiter 3 group priority order set 1) ARB_MODE3 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2) ARB_MODE3 = 1’b1...
Page 253 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY_MODE2 Description Initial State ARB_MODE13 [27] Arbiter 13 group priority mode selection 0 = Fixed ends & Rotate middle 1 = Rotate all ARB_SEL13 [26:24] Arbiter 13 group priority order set 1) ARB_MODE13 = 1’b0...
Page 254 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR PRIORITY_MODE2 Description Initial State ARB_SEL10 [14:12] Arbiter 10 group priority order set 1) ARB_MODE10 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2) ARB_MODE10 = 1’b1...
Page 255 S3C2451X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY UPDATE REGISTER (PRIORITY_UPDATE) Register Address Description Reset Value PRIORITY_ 0x4A000034 IRQ priority update register 0x7F UPDATE1 PRIORITY_ 0x4A000074 IRQ priority update register 0x7F UPDATE2 PRIORITY_UPDATE1 Description Initial State ARB_UPDATE6 Arbiter 6 group priority rotate enable...
Page 256 INTERRUPT CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 10-30 Specifications and information herein are subject to change without notice.
Page 257 S3C2451X RISC MICROPROCESSOR I/O PORTS I/O PORTS OVERVIEW S3C2451X has 174 multi-functional input/output port pins and there are 12 ports as shown below: — Port A(GPA) : 27-output port — Port B(GPB) : 11-input/output port — Port C(GPC) : 16-input/output port —...
Page 258 I/O PORTS S3C2451X RISC MICROPROCESSOR Table 11-1. S3C2451X Port Configuration (Sheet 1) Port A Selectable Pin Functions GPA27 Output only nWE_CF – – GPA26 Output only DQM3 – GPA25 Output only DQM2 – – GPA24 Output only RSMAVD – –...
Page 259 S3C2451X RISC MICROPROCESSOR I/O PORTS Table 11-1. S3C2451X Port Configuration (Sheet 2) (Continued) Port B Selectable Pin Functions GPB10 Input/output nXDREQ0 XDREQ0 I2SSDO_2 GPB9 Input/output nXDACK0 XDACK0 I2SSDO_1 GPB8 Input/output nXDREQ1 XDREQ1 I2CSCL GPB7 Input/output nXDACK1 XDACK1 I2CSDA GPB6 Input/output...
Page 260 I/O PORTS S3C2451X RISC MICROPROCESSOR Table 11-1. S3C2451X Port Configuration (Sheet 3) (Continued) Port D Selectable Pin Functions GPD15 Input/output RGB_VD23 – – GPD14 Input/output RGB_VD22 – – GPD13 Input/output RGB_VD21 – – GPD12 Input/output RGB_VD20 – – GPD11 Input/output RGB_VD19 –...
Page 261 S3C2451X RISC MICROPROCESSOR I/O PORTS Table 11-1. S3C2451X Port Configuration (Sheet 4) (Continued) Port F Selectable Pin Functions GPF7 Input/output EINT7 – – GPF6 Input/output EINT6 – – GPF5 Input/output EINT5 – – GPF4 Input/output EINT4 – – GPF3 Input/output EINT3 –...
Page 262 I/O PORTS S3C2451X RISC MICROPROCESSOR Table 11-1. S3C2451X Port Configuration (Sheet 5) (Continued) Port H Selectable Pin Functions GPH14 Input/output CLKOUT1 – – GPH13 Input/output CLKOUT0 – – GPH12 Input/output EXTUARTCLK – – GPH11 Input/output nRTS1 – – GPH10 Input/output nCTS1 –...
Page 263 S3C2451X RISC MICROPROCESSOR I/O PORTS Table 11-1. S3C2451X Port Configuration (Sheet 6) (Continued) Port K Selectable Pin Functions GPK15 SDATA31 Input/output – – GPK14 Input/output SDATA30 – – GPK13 SDATA29 Input/output – – GPK12 SDATA28 Input/output – GPK11 Input/output SDATA27 –...
Page 264 I/O PORTS S3C2451X RISC MICROPROCESSOR Table 11-1. S3C2451X Port Configuration (Sheet7) (Continued) Port L Selectable Pin Functions GPL14 Input/output – – GPL13 Input/output – – GPL12 SPIMISO1 Input/output – – GPL11 Input/output SPIMOSI1 – – GPL10 Input/output SPICLK1 – –...
Page 265 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPMCON) In S3C2451X, most of the pins are multiplexed pins. So, It is determined which function is selected for each pins. The GPxCON(port control register) determines which function is used for each pin. If GPF0 – GPF7, GPG0 – GPG7 is used for the wakeup signal in Sleep/Stop/DeepStop mode, these ports must be configured in EINT.
Page 266 I/O PORTS S3C2451X RISC MICROPROCESSOR I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS (GPACON, GPADAT) Register Address Description Reset Value GPACON 0x56000000 Configures the pins of port A 0x0fffffff GPADAT 0x56000004 The data register for port A Reserved 0x56000008 Reserved...
Page 267 S3C2451X RISC MICROPROCESSOR I/O PORTS GPA0 0 = Output 1 = RADDR0 PORT A CONTROL REGISTERS (GPACON, GPADAT) (Continued) GPADAT Description Reserved [31:28] Reserved GPA[27:0] [27:0] When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 268 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT B CONTROL REGISTERS (GPBCON, GPBDAT, GPBUDP, GPBSEL) Register Address Description Reset Value GPBCON 0x56000010 Configures the pins of port B GPBDAT 0x56000014 The data register for port B GPBUDP 0x56000018 Pull-up/down control register for port B...
Page 269 S3C2451X RISC MICROPROCESSOR I/O PORTS PORT B CONTROL REGISTERS (GPBCON, GPBDAT, GPBUDP, GPBSEL)(Continued) GPBDAT Description Reserved [31:11] Reserved GPBDAT[10:0] [10:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 270 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT C CONTROL REGISTERS (GPCCON, GPCDAT, GPCUDP) Register Address Description Reset Value GPCCON 0x56000020 Configures the pins of port C GPCDAT 0x56000024 The data register for port C GPCUDP 0x56000028 Pull-up/down control for port C...
Page 271 S3C2451X RISC MICROPROCESSOR I/O PORTS PORT C CONTROL REGISTERS (GPCCON, GPCDAT, GPCUDP) (Continued) GPCDAT Description Reserved [31:16] Reserved GPC[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 272 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT D CONTROL REGISTERS (GPDCON, GPDDAT, GPDUDP) Register Address Description Reset Value GPDCON 0x56000030 Configures the pins of port D GPDDAT 0x56000034 The data register for port D GPDUDP 0x56000038 Pull-up/down control register for port D...
Page 273 S3C2451X RISC MICROPROCESSOR I/O PORTS PORT D CONTROL REGISTERS (GPDCON, GPDDAT, GPDUDP) (Continued) GPDDAT Description Reserved [31:16] Reserved GPD[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit.
Page 274: Sd0_Dat3
I/O PORTS S3C2451X RISC MICROPROCESSOR PORT E CONTROL REGISTERS (GPECON, GPEDAT, GPEUDP, GPESEL) Register Address Description Reset Value GPECON 0x56000040 Configures the pins of port E GPEDAT 0x56000044 The data register for port E GPEUDP 0x56000048 Pull-up/down control register for port E...
Page 275: Pcm0_Sdo
S3C2451X RISC MICROPROCESSOR I/O PORTS PORT E CONTROL REGISTERS (GPECON, GPEDAT, GPEUDP, GPESEL) (Continued) GPEDAT Description Reserved [31:16] Reserved GPE[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 276 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT F CONTROL REGISTERS (GPFCON, GPFDAT, GPFUDP) If GPF0–GPF7 will be used for wake-up signals from Sleep/Stop/Deep Stop mode, the ports will be set in EINT. Register Address Description Reset Value GPFCON 0x56000050 Configures the pins of port F...
Page 277 S3C2451X RISC MICROPROCESSOR I/O PORTS GPFUDP Description Reserved [31:16] Reserved [CPU:CPD] GPFUDP7 [15:14] 00 : pull-up/down disable 01 : pull-down enable GPFUDP0 [1:0] 10 : pull-up enable 11 : not-available 11-21...
Page 278 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT G CONTROL REGISTERS (GPGCON, GPGDAT, GPGUDP) If GPG0–GPG7 will be used for wake-up signals from Sleep/Stop/Deep Stop mode, the ports will be set in EINT. Register Address Description Reset Value GPGCON 0x56000060 Configures the pins of port G...
Page 279 S3C2451X RISC MICROPROCESSOR I/O PORTS PORT G CONTROL REGISTERS (GPGCON, GPGDAT, GPFUDP) (Continued) GPGDAT Description Reserved [31:16] Reserved GPG[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 280 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT H CONTROL REGISTERS (GPHCON, GPHDAT, GPHUDP) Register Address Description Reset Value GPHCON 0x56000070 Configures the pins of port H GPHDAT 0x56000074 The data register for port H GPHUDP 0x56000078 pull-up/down control register for port H...
Page 281 S3C2451X RISC MICROPROCESSOR I/O PORTS PORT H CONTROL REGISTERS (GPHCON, GPHDAT, GPHUDP)(Continued) GPHDAT Description Reserved [31:15] Reserved GPH[14:0] [14:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 282 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT J CONTROL REGISTERS (GPJCON, GPJDAT, GPJUDP, GPJSEL) Register Address Description Reset Value GPJCON 0x560000d0 Configures the pins of port J GPJDAT 0x560000d4 The data register for port J GPJUDP 0x560000d8 pull-up/down control register for port J...
Page 283 S3C2451X RISC MICROPROCESSOR I/O PORTS PORT J CONTROL REGISTERS (GPJCON, GPJDAT, GPJUDP, GPJSEL) (Continued) GPJDAT Description Reserved [31:16] Reserved GPJ[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 284 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT K CONTROL REGISTERS(GPKCON, GPKDAT, GPKUDP) Register Address Description Reset Value GPKCON 0x560000e0 Configures the pins of port K 0xaaaaaaaa GPKDAT 0x560000e4 The data register for port K GPKUDP 0x560000e8 pull-up/down control register for port K...
Page 285 S3C2451X RISC MICROPROCESSOR I/O PORTS GPK0 [1:0] 00 : Input 01 : Output 10 : Sdata[16] 11 : Reserved PORT K CONTROL REGISTERS (GPKCON, GPKDAT, GPKUDP) (Continued) GPKDAT Description GPK[15:0] [31:0] When the port is configured as an input port, the corresponding bit is the pin state.
Page 286: Sd1_Clk
I/O PORTS S3C2451X RISC MICROPROCESSOR PORT L CONTROL REGISTERS (GPLCON, GPLDAT, GPLUDP, GPLSEL) Register Address Description Reset Value GPLCON 0x560000f0 Configures the pins of port L GPLDAT 0x560000f4 The data register for port L GPLUDP 0x560000f8 pull-up/down control register for port L...
Page 287: Pcm1_Sdo
S3C2451X RISC MICROPROCESSOR I/O PORTS PORT L CONTROL REGISTERS (GPLCON, GPLDAT, GPLUDP,GPLSEL) (Continued) GPLDAT Description Reserved [31:15] Reserved GPL[14:0] [14:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit.
Page 288 I/O PORTS S3C2451X RISC MICROPROCESSOR PORT M CONTROL REGISTERS (GPMCON, GPMDAT, GPMUDP) Register Address Description Reset Value GPMCON 0x56000100 Configures the pins of port M GPMDAT 0x56000104 The data register for port M GPMUDP 0x560000108 pull-up/down control register for port M...
Page 289 S3C2451X RISC MICROPROCESSOR I/O PORTS MISCELLANEOUS CONTROL REGISTER (MISCCR) In Sleep mode, the data bus(SD[15:0] or RD[15:0] can be set as Hi-Z and Output ‘0’ state. But, because of the characteristics of IO pad, the data bus pull-up/down resisters have to be turned on or off to reduce the power consumption.
Page 290 I/O PORTS S3C2451X RISC MICROPROCESSOR Reserved Reserved [3:0] NOTE1: User must set first MISCCR[31] = 1’b1 when use the high speed SPI. NOTE2: We recommend not using this output pad to other device’s pll clock source. 11-34...
Page 291 S3C2451X RISC MICROPROCESSOR I/O PORTS DCLK CONTROL REGISTERS (DCLKCON) Register Address Description Reset Value DCLKCON 0x56000084 DCLK0/1 control register DCLKCON Description Reserved [31:28] Reserved DCLK1CMP [27:24] DCLK1 compare value clock toggle value. ( < DCLK1DIV) If the DCLK1CMP is n, Low level duration is( n + 1), High level duration is((DCLK1DIV + 1) –( n +1))
Page 292 I/O PORTS S3C2451X RISC MICROPROCESSOR EXTINTn (External Interrupt Control Register n) The 8 external interrupts can be requested by various Signalling methods. The EXTINT register configures the Signalling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity.
Page 293 S3C2451X RISC MICROPROCESSOR I/O PORTS EINT2 [10:8] Setting the signalling method of the EINT2. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered FLTEN1 Filter enable for EINT1...
Page 294 I/O PORTS S3C2451X RISC MICROPROCESSOR EXTINTn (External Interrupt Control Register n) (Continued) EXTINT1 Description FLTEN15 [31] Filter enable for EINT15 0 = Filter Enable 1= Filter Disable EINT15 [30:28] Setting the signaling method of the EINT15. 000 = Low level...
Page 295 S3C2451X RISC MICROPROCESSOR I/O PORTS EXTINTn (External Interrupt Control Register n) (Continued) EXTINT2 Description Reset Value FLTEN23 [31] Filter enable for EINT23 0 = Filter Enable 1= Filter Disable EINT23 [30:28] Setting the signaling method of the EINT23. 000 = Low level...
Page 296 I/O PORTS S3C2451X RISC MICROPROCESSOR EXTINTn (External Interrupt Control Register n) (Continued) EXTINT2 Description Reset Value FLTEN17 Filter enable for EINT17 0 = Filter Enable 1= Filter Disable EINT17 [6:4] Setting the signalling method of the EINT17. 000 = Low level...
Page 297 S3C2451X RISC MICROPROCESSOR I/O PORTS EINTFLTn (External Interrupt Filter Register n) To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter. Register Address Description Reset Value...
Page 298 I/O PORTS S3C2451X RISC MICROPROCESSOR EINTMASK (External Interrupt Mask Register) Register Address Description Reset Value EINTMASK 0x560000a4 External interrupt mask register 0x00fffff0 EINTMASK Description Reserved [31:24] Reserved EINT23 [23] 0 = enable interrupt 1= masked EINT22 [22] 0 = enable interrupt...
Page 299 S3C2451X RISC MICROPROCESSOR I/O PORTS EINTPEND (External Interrupt Pending Register) Register Address Description Reset Value EINTPEND 0x560000a8 External interrupt pending register EINTPEND Description Reset Value Reserved [31:24] Reserved EINT23 [23] It is cleared by writing “1” 0 = Not occur 1 = Occur interrupt It is cleared by writing “1”...
Page 300 I/O PORTS S3C2451X RISC MICROPROCESSOR GSTATUSn (General Status Registers) Register Address Description Reset Value GSTATUS0 0x560000ac External pin status Not define GSTATUS1 0x560000b0 Device ID 0x32450001 GSTATUS0 Description Reserved [31:4] Reserved nWAIT Status of nWAIT pin NCON Status of NCON pin...
Page 301 S3C2451X RISC MICROPROCESSOR I/O PORTS DSCn (Drive Strength Control) Control the Memory I/O drive strength Register Address Description Reset Value DSC0 0x560000c0 Strength control register 0 0x2aaa_aaaa DSC1 0x560000c4 Strength control register 1 0xaaa_aaaa DSC2 0x560000c8 Strength control register 2...
Page 302 I/O PORTS S3C2451X RISC MICROPROCESSOR DSCn (Drive Strength Control) DSC1 Description Reset Value Reserved [31:28] Reserved DSC_nSCLK [27:26] nSCLK drive strength. 00: 4.9mA 01: 9.8mA 10: 14.8mA 19.7mA DSC_SCLK [25:24] SCLK drive strength. 00: 4.9mA 01: 9.8mA 10: 14.8mA 19.7mA...
Page 303 S3C2451X RISC MICROPROCESSOR I/O PORTS DSCn (Drive Strength Control) DSC2 Description Reset Value Reserved [31:28] Reserved DSC_nFCE [27:26] nFCE drive strength. 00: 5.2mA 01: 10.5mA 10: 15.7mA 21.0mA DSC_nFRE [25:24] nFRE drive strength. 00: 5.2mA 01: 10.5mA 10: 15.7mA 21.0mA...
Page 304 I/O PORTS S3C2451X RISC MICROPROCESSOR DSCn (Drive Strength Control) DSC3 Description Reset Value Reserved [31:10] Reserved DSC_LCD2 [9:8] LCD_VD[23:16] drive strength. 00: 2.6mA 01: 5.2mA 10: 7.8mA 10.5mA DSC_LCD1 [7:6] LCD_VD[15:8] drive strength. 00: 2.6mA 01: 5.2mA 10: 7.8mA 10.5mA...
Page 305 S3C2451X RISC MICROPROCESSOR I/O PORTS PDDMCON (Power Down SDRAM Control Register) Register Address Description Reset Value PDDMCON 0x56000114 Memory I/F control register 0x00411540 PDDMCON Description Reset Value Reserved [31:24] Reserved nSCLK pin status (inactive :”1” ) PSC_nSCLK [23:22] 00 = output 0 01 = output 1...
Page 306 I/O PORTS S3C2451X RISC MICROPROCESSOR PDSMCON (Power Down SRAM Control Register) Register Address Description Reset Value PDSMCON 0x56000118 Memory I/F control register 0x05451500 Description PDSMCON Reset Value Reserved [31:28] Reserved PSC_CF1 [27:26] nREG_CF, nOE_CF, nWE_CF (inactive : “1”) 00 = output 0 01 = output 1...
Page 307 S3C2451X RISC MICROPROCESSOR I/O PORTS RADDR[15:1] pin status (inactive : “0”) PSC_RADDRL [3:2] 00 = output 0 01 = output 1 10 = Hi-Z 11 = Not-Available RADDR[0] pin status (inactive : “0”) PSC_RADDR0 [1:0] 00 = output 0 01 = output 1...
Page 308 I/O PORTS S3C2451X RISC MICROPROCESSOR GPIO Alive & Sleep Part Alive Sleep GPF[7:0], GPG[7:0] GPA, GPB, GPC, GPD, GPE, GPG[15:8], GPH, GPJ, GPK, GPL ,GPM GPACON[27;0], GPADAT[27:0] All registers except alive SFR GPFCON[15;0], GPFDAT[7:0], GPFUDP[15:0] GP*CON, GP*DAT, GP*UDP GPGCONL[15:0], GPGDATL[7:0], GPGUDPL[15:0]...
Page 309 WATCHDOG TIMER OVERVIEW The S3C2451X watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. The watchdog timer generates the reset signal. It can be used as a normal 16-bit interval timer to request interrupt service.
Page 310 CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2451X is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal (DBGACK signal).
Page 311 The Watchdog timer is used to resume the S3C2451X restart on malfunction after its power on. At this time, disable the interrupt generation and enable the Watchdog timer output for reset signal.
Page 312 WATCHDOG TIMER S3C2451X RISC MICROPROCESSOR WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out.
Page 313 OVERVIEW The S3C2451X has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device.
Page 314 PWM TIMER S3C2451X RISC MICROPROCESSOR TOUT0 TCMPB0 TCNTB0 Dead Zone Generator Dead Zone Control Logic0 PCLK 8-Bit TCMPB1 TCNTB1 Prescaler 1/16 TOUT1 TCLK Control Clock Logic1 Divider Dead Zone TCMPB2 TCNTB2 TOUT2 Control Logic2 8-Bit TCMPB3 TCNTB3 Prescaler 1/16 TCLK...
Page 315 S3C2451X RISC MICROPROCESSOR PWM TIMER BASIC TIMER OPERATION Figure 13-2. Timer Operations A timer (except the timer ch-4) has TCNTBn, TCNTn, TCMPBn and TCMPn. The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0.
Page 316 AUTO RELOAD & DOUBLE BUFFERING S3C2451X PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully.
Page 317 S3C2451X RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the internal down-counter(TCNTn) reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit.
Page 318 PWM TIMER S3C2451X RISC MICROPROCESSOR TIMER OPERATION TOUTn Figure 13-4. Example of a Timer Operation The above Figure 13-4 shows the result of the following procedure: 1. Enable the auto re-load function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off).
Page 319 S3C2451X RISC MICROPROCESSOR PWM TIMER PULSE WIDTH MODULATION (PWM) Write Write Write TCMPBn = 60 TCMPBn = 40 TCMPBn = 30 Write Write Write TCMPBn = 50 TCMPBn = 30 TCMPBn = Next PWM Value Figure 13-5. Example of PWM PWM function can be implemented by using the TCMPBn.
Page 320 PWM TIMER S3C2451X RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 13-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1.
Page 321 S3C2451X RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The Dead Zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time.
Page 322 PWM TIMER S3C2451X RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive.
Page 323 S3C2451X RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address Description Reset Value...
Page 324 PWM TIMER S3C2451X RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address Description Reset Value TCFG1 0x51000004 5-MUX & DMA mode selection register 0x00000000 TCFG1 Description Initial State Reserved [31:24] 00000000 DMA mode [23:20] Select DMA request channel 0000 0000 = No select (all interrupt) 0001 = Timer0...
Page 325 S3C2451X RISC MICROPROCESSOR PWM TIMER TIMER CONTROL (TCON) REGISTER Register Address Description Reset Value TCON 0x51000008 Timer control register 0x00000000 TCON Description Initial state Timer 4 auto reload [22] Determine auto reload on/off for Timer 4. on/off 0 = One-shot...
Page 326 PWM TIMER S3C2451X RISC MICROPROCESSOR TIMER CONTROL (TCON) REGISTER (Continued) TCON Description Initial state Reserved [7:5] Reserved Dead zone enable Determine the dead zone operation. 0 = Disable 1 = Enable Timer 0 auto reload Determine auto reload on/off for Timer 0.
Page 327 S3C2451X RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register Address Description Reset Value TCNTB0 0x5100000C Timer 0 count buffer register 0x00000000 TCMPB0 0x51000010 Timer 0 compare buffer register 0x00000000 TCMPB0 Description Initial State...
Page 328 PWM TIMER S3C2451X RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register Address Description Reset Value TCNTB1 0x51000018 Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C Timer 1 compare buffer register 0x00000000 TCMPB1 Description Initial State...
Page 329 S3C2451X RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register Address Description Reset Value TCNTB2 0x51000024 Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 Timer 2 compare buffer register 0x00000000 TCMPB2 Description Initial State...
Page 330 PWM TIMER S3C2451X RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register Address Description Reset Value TCNTB3 0x51000030 Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 Timer 3 compare buffer register 0x00000000 TCMPB3 Description Initial State...
Page 331 S3C2451X RISC MICROPROCESSOR PWM TIMER TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address Description Reset Value TCNTB4 0x5100003C Timer 4 count buffer register 0x00000000 TCNTB4 Description Initial State Timer 4 count buffer register [15:0] Set count buffer value for Timer 4...
Page 332 PWM TIMER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 13-20 Specifications and information herein are subject to change without notice.
Page 333 Real Time Clock REAL TIME CLOCK (RTC) This chapter describes the functions and usage of Real Time Clock (RTC) in S3C2451X RISC microprocessor. 14.1 Overview The Real Time Clock (RTC) unit can be operated by the backup battery when the system power is off. The data include the time by second, minute, hour, date, day, month, and year.
Page 334 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.3 Real Time Clock Operation Description TICWKUP TICNT Time Tick Generator TICINT 32KHz~1Hz RTCRST Clock Reset Leap Year Generator Divider Register XTIrtc 1 Hz HOUR DATE YEAR XTOrtc Control Alarm Generator Register RTCCON RTCALM ALMWKUP ALMINT Figure 14-1.
Page 335 S3C2451 RISC MICROPROCESSOR Real Time Clock 14.3.2 Read/Write Register Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, day, date, month, and year, the CPU must read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDATE, BCDDAY, BCDMON, and BCDYEAR registers respectively in the RTC block.
Page 336 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.3.5 Tick time interrupt The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches ‘0’ when the tick time interrupt occurs. Then the period of interrupt is as follows: Tick clock frequency (Hz) = RTC clock / 2 n: RTC clock divide value(decided by RTCCON[8:4] )
Page 337 S3C2451 RISC MICROPROCESSOR Real Time Clock cnt15 Q15N RTC clock (32. 768KHz) RTCCON [8:5] rtcif 2. 048KHz Counter Tick interrupt Compare RTCCON [4] TICK TIME COUNT REGISTER TICCNT2[16:0] TICCNT0[6:0] TICCNT1[7:0] Tick time interrupt enable (1bit) Figure 14-2. RTC tick interrupt clock scheme Example) For 1 ms Tick interrupt generation.
Page 338 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.3.6 32.768 KHz X-TAL Connection EXAMPLE The Figure 14-3 shows a circuit of the RTC unit oscillation at 32.768 Khz. VDD_RTC 15~22pF XTIRTC XTIRTC 5Mohm 32768Hz XTORTC XTORTC 15~22pF B) RTC Block is not used A) RTC Block is used Figure 14-3.
Page 339 S3C2451 RISC MICROPROCESSOR Real Time Clock 14.5 Register Description 14.5.1 Memory Map Register Address Description Reset Value RTCCON 0x57000040 RTC control Register 0x00 TICNT0 Tick time count Register0 0x57000044 TICNT1 0x5700004C Tick time count Register1 TICNT2 0x57000048 Tick time count Register2 RTCALM 0x57000050 RTC alarm control Register...
Page 340 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.6 Individual Register Descriptions 14.6.1 REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 9 bits . It controls the read/write enable of the CLKSEL, CNTSEL and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, Therefore it must be set to 1 in an RTC control routine to enable data read/write after a system reset.
Page 341 14.6.2 Tick Time Count Register 0 (TICNT0) The TICNT0 register determines tick interrupt enable and tick counter value S3C2451X supports 32bits tic time counter. So, from 14 to 8bits of 32bit tick time count value is selected at TICNT0 register (TICNT0[6:0]).
Page 342 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.6.5 RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and ALMWKUP as power mode. For using ALMINT and ALMWKUP, ALMEN must be enable.
Page 343 S3C2451 RISC MICROPROCESSOR Real Time Clock 14.6.6 ALARM SECOND DATA (ALMSEC) REGISTER Register Address Description Reset Value ALMSEC 0x57000054 Alarm second data Register ALMSEC Description Initial State Reserved SECDATA [6:4] BCD value for alarm second. 0 ~ 5 [3:0] 0 ~ 9 0000 14.6.7 ALARM MIN DATA (ALMMIN) REGISTER Register...
Page 344 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.6.9 ALARM DATE DATA (ALMDAte) REGISTER Register Address Description Reset Value ALMDATE 0x57000060 Alarm day data Register 0x01 ALMDATE Description Initial State Reserved [7:6] DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31. 0 ~ 3 [3:0] 0 ~ 9...
Page 345 S3C2451 RISC MICROPROCESSOR Real Time Clock 14.6.12 BCD SECOND (BCDSEC) REGISTER Register Address Description Reset Value BCDSEC 0x57000070 BCD second Register Undefined BCDSEC Description Initial State SECDATA [6:4] BCD value for second. 0 ~ 5 [3:0] 0 ~ 9 14.6.13 BCD MINUTE (BCDMIN) REGISTER Register Address Description...
Page 346 S3C2451 Real Time Clock RISC MICROPROCESSOR 14.6.14 BCD HOUR(BCDHOUR) REGISTER Register Address Description Reset Value BCDHOUR 0x57000078 BCD hour Register Undefined BCDHOUR Description Initial State Reserved [7:6] HOURDATA [5:4] BCD value for hour. 0 ~ 2 [3:0] 0 ~ 9 14.6.15 BCD DATE (BCDDATE) REGISTER Register Address...
Page 347 S3C2451 RISC MICROPROCESSOR Real Time Clock 14.6.17 BCD MONTH (BCDMON) REGISTER Register Address Description Reset Value BCDMON 0x57000084 BCD month Register Undefined BCDMON Description Initial State Reserved [7:5] MONDATA BCD value for month. 0 ~ 1 [3:0] 0 ~ 9 14.6.18 BCD YEAR (BCDYEAR) REGISTER Register Address...
Page 348 S3C2451 Real Time Clock RISC MICROPROCESSOR NOTES 14-16 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
Page 349 UART can support bit rates up to 3Mbps bps. Each UART channel contains two 64-byte FIFOs for receiver and transmitter. The S3C2451X UART includes programmable baud rates, infrared (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Page 350 UART S3C2451 RISC MICROPROCESSOR BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter TXDn Control Buad-rate Clock Source Unit Generator (PCLK, FCLK/n,UEXTCLK) Receiver Receive Shifter RXDn Receive Holding Register (Non-FIFO mode only) Receive Buffer Register(64 Byte)
Page 351 S3C2451 RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infrared mode, and auto flow control. Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn).
Page 352 Auto Flow Control (AFC) The S3C2451X's UART 0, UART 1 and UART 2 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software.
Page 353 AFC does not support the RS-232C interface. Interrupt/DMA Request Generation Each UART of the S3C2451X has seven status (Tx/Rx/Error) signals: Overrun error, Parity error, Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn).
Page 354 UART S3C2451 RISC MICROPROCESSOR UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out.
Page 355 Loopback Mode The S3C2451X UART provides a test mode referred to as the Loopback mode, to aid in isolating faults in the communication link. This mode structurally enables the connection of RXD and TXD in the UART. In this mode, therefore, transmitted data is received to the receiver, via RXD.
Page 356 UART S3C2451 RISC MICROPROCESSOR Figure 15-5. Serial I/O Frame Timing Diagram (Normal UART) Figure 15-6. Infrared Transmit Mode Frame Timing Diagram Figure 15-7. Infrared Receive Mode Frame Timing Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 15-8 Specifications and information herein are subject to change without notice.
Page 357 S3C2451 RISC MICROPROCESSOR UART UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are four UART line control registers including ULCON0, ULCON1, ULCON2 and ULCON3 in the UART block. Register Address Description Reset Value ULCON0 0x50000000 UART channel 0 line control register 0x00 ULCON1 0x50004000...
Page 358 UART S3C2451 RISC MICROPROCESSOR UART CONTROL REGISTER There are four UART control registers including UCON0, UCON1, UCON2 and UCON3 in the UART block. Register Address Description Reset Value UCON0 0x50000004 UART channel 0 control register 0x00 UCON1 0x50004004 UART channel 1 control register 0x00 UCON2 0x50008004...
Page 359 S3C2451 RISC MICROPROCESSOR UART UART CONTROL REGISTER (Continued) UCONn Description Initial State Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register. 00 = Disable 01 = Interrupt request or polling mode 10 = DMA request( request signal 0) 11 = DMA request( request signal 1) Receive Mode...
Page 360 UART S3C2451 RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are four UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART block. Register Address Description Reset Value UFCON0 0x50000008 UART channel 0 FIFO control register UFCON1 0x50004008 UART channel 1 FIFO control register UFCON2 0x50008008...
Page 361 1 = 'L' level (Activate nRTS) NOTES: UART 3 does not support AFC function, because the S3C2451X has no nRTS3 and nCTS3. If AFC bit is enabled and Time-out bit is disabled, RTS trigger level must be lager than Rx FIFO trigger level.
Page 362 UART S3C2451 RISC MICROPROCESSOR UART TX/RX STATUS REGISTER There are four UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in the UART block. Register Address Description Reset Value UTRSTAT0 0x50000010 UART channel 0 Tx/Rx status register UTRSTAT1 0x50004010 UART channel 1 Tx/Rx status register UTRSTAT2 0x50008010...
Page 363 S3C2451 RISC MICROPROCESSOR UART UART ERROR STATUS REGISTER There are four UART Rx error status registers including UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3 in the UART block. Register Address Description Reset Value UERSTAT0 0x50000014 UART channel 0 Rx error status register UERSTAT1 0x50004014 UART channel 1 Rx error status register...
Page 364 UART S3C2451 RISC MICROPROCESSOR UART FIFO STATUS REGISTER There are four UART FIFO status registers including UFSTAT0, UFSTAT1 UFSTAT2 and UFSTAT3 in the UART block. Register Address Description Reset Value UFSTAT0 0x50000018 UART channel 0 FIFO status register 0x00 UFSTAT1 0x50004018 UART channel 1 FIFO status register 0x00...
Page 365 Undef UMSTAT0 Description Initial State Delta CTS Indicate that the nCTS input to the S3C2451X has changed state since the last time it was read by CPU. (Refer to Figure 15-8.) 0 = Has not changed 1 = Has changed...
Page 366 UART S3C2451 RISC MICROPROCESSOR UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are four UART transmit buffer registers including UTXH0, UTXH1, UTXH2 and UTXH3 in the UART block. UTXHn has an 8-bit data for transmission data. Register Address Description Reset Value UTXH0...
Page 367 Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2451X's internal system clock or EXTUARTCLK. Clock frequencies of 16 times the baud rate are used for sampling serial data to minimize error. Clock of 16 times baud- rate is generated by dividing the source clock(PCLK or divided EPLL clock or EXTUARTCLK).
Page 368 UART S3C2451 RISC MICROPROCESSOR Table 15-2 Recommended value table of DIVSLOTn register Floating point part Num of 1’s UDIVSLOTn 0x0000(0000_0000_0000_0000b) 0.0625 0x0080(0000_0000_0000_1000b) 0.125 0x0808(0000_1000_0000_1000b) 0.1875 0x0888(0000_1000_1000_1000b) 0.25 0x2222(0010_0010_0010_0010b) 0.3125 0x4924(0100_1001_0010_0100b) 0.375 0x4A52(0100_1010_0101_0010b) 0.4375 0x54AA(0101_0100_1010_1010b) 0x5555(0101_0101_0101_0101b) 0.5625 0xD555(1101_0101_0101_0101b) 0.625 0xD5D5(1101_0101_1101_0101b) 0.6875 0xDDD5(1101_1101_1101_0101b) 0.75 0xDDDD(1101_1101_1101_1101b)
Page 369 S3C2451 RISC MICROPROCESSOR UART Register Address Description Reset Value UBRDIV0 0x50000028 Baud rate divisior(integer place) register 0 – UBRDIV1 0x50004028 Baud rate divisior(integer place) register 1 – UBRDIV2 0x50008028 Baud rate divisior(integer place) register 2 – UBRDIV3 0x5000C028 Baud rate divisior(integer place) register 3 –...
Page 370 UART S3C2451 RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 15-22 Specifications and information herein are subject to change without notice.
Page 371 S3C2451X RISC MICROPROCESSOR USB HOST CONTROLLER USB HOST CONTROLLER OVERVIEW S3C2451X supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.1 compatible • Two down stream ports • Support for both LowSpeed and FullSpeed USB devices...
Page 372 USB HOST CONTROLLER S3C2451X RISC MICROPROCESSOR USB HOST CONTROLLER SPECIAL REGISTERS The S3C2451X USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detail information. Table 16-1. OHCI Registers for USB Host Controller...
Page 373 USB 2.0 FUNCTION OVERVIEW The Samsung USB 2.0 Controller is designed to aid the rapid implementation of the USB 2.0 peripheral device. The controller supports both High and Full speed mode. Using the standard UTMI interface and AHB interface the USB 2.0 Controller can support up to 9 Endpoints (including Endpoint0) with programmable Interrupt, Bulk mode.
Page 374 Status Registers. And also Function has an AHB Master to enable the link to transfer data on the AHB. The S3C2451x USB system shown as Figure 17-1, can be configured as following : 1. USB 1.1 Host 1 Port & USB 2.0 Device 1 Port 2.
Page 375 USB2.0 DEVICE TO ACTIVATE USB PORT1 FOR USB 2.0 FUNCTION USB Function block of S3C2451X shares USB PORT1 with USB Host block. To activate USB PORT1 for USB Function, see USB control registers in System Controller Guide AHB Slave Interface...
Page 376 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS The USB 2.0 controller includes several 16-bit registers for the endpoint programming and debugging. The registers can be grouped into two categories. Few of the indexed registers are related to endpoint 0, but most of them are utilized for the control and status monitoring of each data endpoint, including FIFO control and packet size configuration.
Page 377 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE Table 17-2. Indexed Registers Register Address Description 0x4980_002C Endpoints Status Register 0x4980_0030 Endpoints Control Register BRCR 0x4980_0034 Byte Read Count Register BWCR 0x4980_0038 Byte Write Count Register 0x4980_003C Max Packet Register 0x4980_0040 DMA Control Register...
Page 378 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR REGISTERS INDEX REGISTER (IR) The index register is used for indexing a specific endpoint. In most cases, setting the index register value should precede any other operation. Register Address Description Reset Value 0x4980_0000 Index Register...
Page 379 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE ENDPOINT INTERRUPT REGISTER (EIR) The endpoint interrupt register lets the MCU knows what endpoint generates the interrupt. The source of an interrupt could be various, but, when an interrupt is detected, the endpoint status register should be checked to identify if it’s related to specific endpoint.
Page 380 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR ENDPOINT INTERRUPT ENABLE REGISTER (EIER) Pairing with interrupt register, this register enables interrupt for each endpoints. Register Address Description Reset Value EIER 0x4980_0008 Endpoint Interrupt Enable Register 0x00 EIER Description Initial State [31:9] Reserved EP8IE...
Page 381 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE FUNCTION ADDRESS REGISTER (FAR) This register holds the address of USB device. Register Address Description Reset Value 0x4980_000C Function Address Register Description Initial State [31:7] Reserved [6:0] MCU can read a unique USB function address from this 7’h0...
Page 382 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR ENDPOINT DIRECTION REGISTER (EDR) USB 2.0 Core supports IN/OUT direction control for each endpoint. This direction can’t be changed dynamically. Only by new enumeration, the direction can be altered. Since the endpoint 0 is bi-directional, there is no direction bit assigned to it.
Page 383 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE TEST REGISTER (TR) The test register is used for the diagnostics. All bit are activated when 1 is written to and is cleared by 0 on them. Bit[3:0] are for the high speed device only.
Page 384 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR SYSTEM STATUS REGISTER (SSR) This register reports operational status of the USB 2.0 Function Core, especially about error status and power saving mode status. Except the line status, every status bits in the System Status Register could be an interrupt sources.
Page 385 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE Description Initial State DM Data Line State DM informs the status of D- Line Host Speed 0 = Full Speed 1 = High Speed Speed Detection End. SDE is set by the core when the HS Detect Handshake process is ended.
Page 386 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR SYSTEM CONTROL REGISTER (SCR) This register enables top-level control of the core. MCU should access this register for controls such as Power saving mode enable/disable. Register Address Description Reset Value 0x4980_0020 System Control Register Description...
Page 387 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE Description Initial State Should be zero Speed detection Control SPDC Software can reset Speed detection Logic through this bit. This bit is used to control speed detection process in case of System with a long initial time.
Page 388 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR EP0 STATUS REGISTER (EP0SR) This register stores status information of the Endpoint 0. These status information are set automatically by the core when corresponding conditions are met. After reading the bits, MCU should write 1 to clear them.
Page 389 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE EP0 CONTROL REGISTER (EP0CR) EP0 control register is used for the control of endpoint 0. Controls such as enabling ep0 related interrupts and toggle controls can be handled by EP0 control register. Register Address Description...
Page 390 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR ENDPOINT# BUFFER REGISTER (EP#BR) The buffer register is used to hold data for TX/RX transfer. Register Address Description Reset Value EP0BR 0x4980_0060 EP0 Buffer Register EP1BR 0x4980_0064 EP1 Buffer Register EP2BR 0x4980_0068 EP2 Buffer Register...
Page 391 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE ENDPOINT STATUS REGISTER (ESR) The endpoint status register reports current status of an endpoint (except EP0) to the MCU Register Address Description Reset Value 0x4980_002C Endpoint Status Register Description Initial State [31:12] Reserved FPID [11] First OUT Packet interrupt Disable in OUT DMA operation.
Page 392 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR Description Initial State FIFO Flushed. FFS informs that FIFO is flushed. This bit is an interrupt source. This bit is cleared when the MCU clears FLUSH bit in Endpoint Control Register. Function Stall Condition. FSC informs that STALL handshake due to functional stall condition is sent to Host.
Page 393 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE ENDPOINT CONTROL REGISTER (ECR) The endpoint control register is useful for controlling an endpoint both in normal operation and test case. Putting an endpoint in specific operation mode can be accomplished through the endpoint control register.
Page 394 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR Description Initial State Endpoint Stall Set ESS is set by the MCU when the MCU intends to send STALL handshake to Host. This bit is cleared when the MCU writes 0 in it. Interrupt Endpoint Mode Set IEMS IEMS determines the transfer type of an endpoint.
Page 395 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE BYTE READ COUNT REGISTER (BRCR) The byte read count register keeps byte (half word) counts of a RX packet from USB host. Register Address Description Reset Value BRCR 0x4980_0034 Byte Read Count Register BRCR Description...
Page 396 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR BYTE WRITE COUNT REGISTER (BWCR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet.
Page 397 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE MAX PACKET REGISTER (MPR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet.
Page 398 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR DMA CONTROL REGISTER (DCR) The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register. Register Address Description Reset Value 0x4980_0040 DMA Control Register Description Initial State [31:6] Reserved ARDRD Auto Rx DMA Run set disable.
Page 399 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE DMA TRANSFER COUNTER REGISTER (DTCR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet.
Page 400 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR DMA FIFO COUNTER REGISTER (DFCR) This register has the byte number of data per DMA operation. The max packet size is loaded in this register. Register Address Description Reset Value DFCR 0x4980_0048 DMA FIFO Counter Register...
Page 401 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE DMA TOTAL TRANSFER COUNTER REGISTER 1/2 (DTTCR 1/2) This register has the total byte number of data to transfer using DMA Interface. When this counter register value is zero, DMA operation is ended. Register Address...
Page 402 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR DMA INTERFACE CONTROL REGISTER (DICR) The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register. Register Address Description Reset Value DICR 0x4980_0084 DMA Interface Counter Register DICR Description...
Page 403 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE MEMORY BASE ADDRESS REGISTER (MBAR) Register Address Description Reset Value MBAR 0x4980_0088 Memory Base Address Register MBAR# Description Initial State MBAR [31:0] This register should have memory base address to be 32’h0 transferred using DMA Interface.
Page 404 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR MEMORY CURRENT ADDRESS REGISTER (MCAR) Register Address Description Reset Value MCAR 0x4980_008C Memory Current Address Register MCAR# Description Initial State MCAR [31:0] This register should have memory current address to be transferred using DMA Interface.
Page 405 S3C2451X RISC MICROPROCESSOR USB2.0 DEVICE AHB MASTER(DMA) OPERATION FLOW CHART A. OUT Transfer Operation Flow AHB Master IF Registers (Unit Counter, Total Transfer Counter, Control) are set in initial state or Interrupt service routine. AHB Master IF Registers are to be set after MCU reads all data packets from USB OUT FIFO to operate a AHB Master operation after interrupt service mode.
Page 406 USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR B. IN Transfer Operation Flow AHB Master Registers( Unit Counter, Total Transfer Counter, Control) are set in intial state or Interrupt service routine. AHB Master Registers are to be set after MCU writes one packet data...
Page 407 In multi-master IIC-bus mode, multiple S3C2451X RISC microprocessors can receive or transmit serial data to or from slave devices. The master S3C2451X can initiate and terminate a data transfer over the IIC-bus. The IIC-bus in the S3C2451X uses Standard bus arbitration procedure.
Page 408 IIC-BUS INTERFACE S3C2451X RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic IICCON IICSTAT PCLK 4-bit Prescaler Shift Register Shift Register (IICDS) Data Bus Figure 18-1. IIC-Bus Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 409 S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE The S3C2451X IIC-bus interface has four operation modes: — Master transmitter mode — Master receive mode — Slave transmitter mode — Slave receive mode Functional relationships among these operating modes are described below.
Page 410 IIC-BUS INTERFACE S3C2451X RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode.
Page 411 S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE Acknowledgement Acknowledgement Signal from Receiver Signal from Receiver Byte Complete, Interrupt Clock Line Held Low by within Receiver receiver and/or transmitter Figure 18-4. Data Transfer on the IIC-Bus ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line.
Page 412 In Receive mode, when data is received, the IIC-bus interface will wait until IICDS register is read. Before the new data is read out, the SCL line will be held low and then released after it is read. The S3C2451X should hold the interrupt to identify the completion of the new data reception.
Page 413 S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1. Write own slave address on IICADD register, if needed. 2. Set IICCON register. a) Enable interrupt b) Define SCL period 3.
Page 414 IIC-BUS INTERFACE S3C2451X RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Stop?
Page 415 S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Write data to IICDS.
Page 416 IIC-BUS INTERFACE S3C2451X RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? The IIC address match interrupt is generated. Read data from IICDS.
Page 417 S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address Description Reset Value IICCON0 0x54000000 IIC0-Bus control register 0x0X IICCON1 0x54000100 IIC1-Bus control register 0x0X IICCON0 Description Initial State IICCON1 Acknowledge IIC-bus acknowledge enable bit.
Page 418 IIC-BUS INTERFACE S3C2451X RISC MICROPROCESSOR MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address Description Reset Value IICSTAT0 0x54000004 IIC0-Bus control/status register IICSTAT1 0x54000104 IIC1-Bus control/status register IICSTAT0 Description Initial State IICSTAT1 Mode selection [7:6] IIC-bus master/slave Tx/Rx mode select bits. 00: Slave receive mode...
Page 419 S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address Description Reset Value IICADD0 0x54000008 IIC0-Bus address register 0xXX IICADD1 0x54000108 IIC1-Bus address register 0xXX IICADD0 Description Initial State IICADD1 Slave address [7:0] 7-bit slave address, latched from the IIC-bus.
Page 420 IIC-BUS INTERFACE S3C2451X RISC MICROPROCESSOR MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register Address Description Reset Value IICLC0 0x54000010 IIC0-Bus multi-master line control register 0x00 IICLC1 0x54000110 IIC1-Bus multi-master line control register 0x00 IICLC0 Description Initial State IICLC1 Filter enable IIC-bus filter enable bit.
Page 421 S3C2451X RISC MICROPROCESSOR INTRODUCTION 2D graphics accelerator supports three types of primitive drawings: Line/Point Drawing, Bit Block Transfer (BitBLT) and Color Expansion (Text Drawing). Rendering a primitive takes two steps: 1) configure the rendering parameters, such as foreground color and the coordinate data, by setting the drawing-context registers;...
Page 422 S3C2451X RISC MICROPROCESSOR COLOR FORMAT CONVERSION 2D supports seven color formats: RGB_565, RGBA_5551, ARGB_1555, RGBA_8888, ARGB_8888, XRGB_8888, and RGBX_8888. The structure of each color format is illustrated in Figure 19-1. RGB_565 RGBA_5551 15 14 ARGB_1555 RGBA_8888 ARGB_8888 XRGB_8888 0xFF RGBX_8888 0xFF Figure 19-1.
Page 423 S3C2451X RISC MICROPROCESSOR YUV422 2-Planar Figure 19-2. YUV 2-Planar Format COMMAND FIFO 2D has a 32-word command FIFO. Every data written to command registers and parameter setting registers will be written to the FIFO first. If the graphics engine is idle (no command is being executed), the data will be written to the designated register in one cycle;...
Page 424 S3C2451X RISC MICROPROCESSOR Line/Point Drawing Line Drawing renders a line between the starting point (sx, sy) and the ending point (ex, ey) specified by the user. If the distance of these two points along y axis is greater than that along x axis ( |ey - sy| > |ex - sx| ), the Major Axis should be set to y-axis;...
Page 425 S3C2451X RISC MICROPROCESSOR Off-Screen Rendering Off-screen bit block transfer copies pixel data from off-screen memory to frame buffer. Color space conversion is performed automatically if SRC_COLOR_MODE differs from DEST_COLOR_MODE. YUV 4:2:2 input is also supported. Transparent Mode 2D can render image in Transparent Mode. In this mode, the pixels having the same color with background color (BG_COLOR) are discarded, resulting in a transparent effect.
Page 426 S3C2451X RISC MICROPROCESSOR DEST_BASE_ADDR The base address of the destination image (usually the frame buffer base address) SRC_HORI_RES_REG The horizontal resolution of the source image SRC_VERT_RES_REG The vertical resolution of the source image (used in YUV mode) SC_HORI_RES_REG The screen resolution...
Page 427 S3C2451X RISC MICROPROCESSOR Figure 19-6 Color Expansion 2D can render Color Expansion image in Transparent Mode. In this mode, the pixels with background color (the corresponding bits are ‘0’s) are discarded, resulting in a transparent effect. The transparent effect on Color Expansion is illustrated in Figure 19-7, in which the lower three lines are drawn with Transparent Mode enabled while the upper three disabled.
Page 428 S3C2451X RISC MICROPROCESSOR ROTATION The pixels can be rotated around the reference point (ox, oy) by 90/180/270 degree clockwise or perform a X- axis/Y-axis flip around the horizontal or vertical line on which (ox, oy) lies. The effects of all rotation options are summarized in the following table and illustrated in Figure 19-8.
Page 429 S3C2451X RISC MICROPROCESSOR CLIPPING Clipping discards the pixels (after rotation) outside the clipping window. The discarded pixels will not go through the rest of rendering pipelines. Note that the clipping windows must reside totally inside the screen. Setting the clipping window the same size with the screen will disable the clipping effect, and a clipping window bigger than the screen size is not allowed.
Page 430 S3C2451X RISC MICROPROCESSOR Bit5 Bit6 Bit7 The third operand can be pattern or foreground color, configurable by the OS bit in the ROP_REG. Pattern is a user-specified 8x8x16-bpp image; the pattern data should be given in RGB565 format. The following equation is used to calculate the pattern index of pixel (x, y): index = ( ((patternOffsetY + y) &...
Page 431 S3C2451X RISC MICROPROCESSOR Per-pixel alpha blending: ALPHA (given by the source image, from 0 to 255) [Alpha Blending] data = ( source * (ALPHA+1) + destination * (255-ALPHA) ) >> 8 [Fading] data = ((source * (ALPHA+1) ) >> 8 ) + fading offset...
Page 432 S3C2451X RISC MICROPROCESSOR REGISTER DESCRIPTIONS Register Offset Description Reset Value General Registers CONTROL_REG 0x0000 Control register. 0x0000_0000 INTEN_REG 0x0004 Interrupt Enable register. 0x0000_0000 FIFO_INTC_REG 0x0008 Interrupt Control register. 0x0000_0018 INTC_PEND_REG 0x000C Interrupt Control Pending register. 0x0000_0000 FIFO_STAT_REG 0x0010 Command FIFO Status register.
Page 433 S3C2451X RISC MICROPROCESSOR CW_RB_Y_REG 0x0238 Bottom Y coordinate of Clip Window. 0x0000_0000 Coordinates COORD0_REG 0x0300 Coordinates 0 register. 0x0000_0000 COORD0_X_REG 0x0304 X coordinate of Coordinates 0. 0x0000_0000 COORD0_Y_REG 0x0308 Y coordinate of Coordinates 0. 0x0000_0000 COORD1_REG 0x0310 Coordinates 1 register.
Page 434 S3C2451X RISC MICROPROCESSOR STENCIL_CNTL_REG 0x0720 Stencil control register 0x0000_0000 STENCIL_DR_MIN_REG 0x0724 Stencil decision reference MIN register 0x0000_0000 STENCIL_DR_MAX_REG 0x0728 Stencil decision reference MAX register 0xFFFF_FFFF Image Base Address SRC_BASE_ADDR_REG 0x0730 Source Image Base Address register 0x0000_0000 DEST_BASE_ADDR_REG 0x0734 Dest Image Base Address register (in most...
Page 435 S3C2451X RISC MICROPROCESSOR General Registers CONTROL REGISTER(CONTROL_REG) Register Address Description Reset Value CONTROL_REG 0x4D408000 Control register Field Description Initial State Reserved [31:1] Software Reset Write to this bit results in a one-cycle reset signal to FIMG2D graphics engine. Every command register and parameter setting register will be assigned the “Reset Value”, and the command FIFO...
Page 436 S3C2451X RISC MICROPROCESSOR FIFO INTERRUPT CONTROL REGISTER (FIFO_INTC_REG) Register Address Description Reset Value FIFO_INTC_REG 0x4D408008 FIFO Interrupt Control 0x18 Field Description Initial State Reserved [31:6] FIFO_INT_LEVEL [5:0] If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED (in 0x18 FIFO_STAT_REG) is greater or equal to FIFO_INT_LEVEL, an interrupt occurs.
Page 437 S3C2451X RISC MICROPROCESSOR 1: Graphics engine is in idle state. The graphics engine finishes the ALL_FIN execution of all commands in the command FIFO. Note that ALL_FIN = CMD_FIN && (FIFO_USED==0). 0: In the middle of rendering process, or FIFO_USED is greater than 0.
Page 438 S3C2451X RISC MICROPROCESSOR COMMAND REGISTERS LINE DRAWING REGISTER (CMD0_REG) Register Address Description Reset Value CMD0_REG 0x4D408100 Line Drawing Register Field Description Initial State Reserved [31:10] 0 : Draw Last Point 1 : Do-not-Draw Last Point. 0 : Major axis is Y.
Page 439 S3C2451X RISC MICROPROCESSOR bpp (e.g., RGB565), the upper 16 bits of the data are ignored. HOST TO SCREEN CONTINUE BitBLT REGISTER (CMD3_REG) Register Address Description Reset Value CMD3_REG 0x4D40810C Host to Screen Continue BitBLT Register Field Description Initial State Data...
Page 440 S3C2451X RISC MICROPROCESSOR Parameter Setting Registers Resolution SOURCE IMAGE RESOLUTION REGISTER (SRC_RES_REG) Register Address Description Reset Value SRC_RES_REG 0x4D408200 Source Image Resolution Register Field Description Initial State Reserved [31:27] VertRes [26:16] Vertical resolution of source image. Range: 1 ~ 2040...
Page 441 S3C2451X RISC MICROPROCESSOR SCREEN RESOLUTION REGISTER (SC_RES_REG) Register Address Description Reset Value SC_RES_REG 0x4D408210 Screen Resolution Register Field Description Initial State Reserved [31:27] VertRes [26:16] Vertical resolution of the screen. Range: 1 ~ 2040 Reserved [15:11] HoriRes [10:0] Horizontal resolution of the screen.
Page 442 S3C2451X RISC MICROPROCESSOR Clipping Window LEFTTOP CLIPPING WINDOW REGISTER (CW_LT_REG) Register Address Description Reset Value CW_LT_REG 0x4D408220 LeftTop Clipping Window Register Field Description Initial State Reserved [31:27] TopCW_Y [26:16] Top Y Clipping Window Requirement: TopCW_Y < BottomCW_Y Reserved [15:11] LeftCW_X [10:0] Left X Coordinate of Clipping Window.
Page 443 S3C2451X RISC MICROPROCESSOR RIGHTBOTTOM CLIPPING WINDOW REGISTER (CW_RB_REG) Register Address Description Reset Value CW_RB_REG 0x4D408230 RightBottom Clipping Window Register Field Description Initial State Reserved [31:27] BottomCW_Y [26:16] Bottom Y Clipping Window Requirement: BottomCW_Y < VeriRes (SC_VERI_RES_REG) Reserved [15:11] RightCW_X [10:0] Right X Clipping Window Requirement: RightCW_X <...
Page 444 S3C2451X RISC MICROPROCESSOR Coordinates COORDINATE_0 REGISTER (COORD0_REG) Register Address Description Reset Value COORD0_REG 0x4D408300 Coordinate_0 Register Field Description Initial State Reserved [31:27] [26:16] Coordinate_0 Y Range: 0 ~ 2039 Reserved [15:11] [10:0] Coordinate_0 X Range: 0 ~ 2039 COORDINATE_0 X REGISTER (COORD0_X_REG)
Page 445 S3C2451X RISC MICROPROCESSOR COORDINATE_1 REGISTER (COORD1_REG) Register Address Description Reset Value COORD1_REG 0x4D408310 Coordinate_1 Register Field Description Initial State Reserved [31:27] [26:16] Coordinate_1 Y Range: 0 ~ 2039 Reserved [15:11] [10:0] Coordinate_1 X Range: 0 ~ 2039 COORDINATE_1 X REGISTER (COORD1_X_REG)
Page 446 S3C2451X RISC MICROPROCESSOR Field Description Initial State Reserved [31:27] [26:16] Coordinate_2 Y Range: 0 ~ 2039 Reserved [15:11] [10:0] Coordinate_2 X Range: 0 ~ 2039 COORDINATE_2 X REGISTER (COORD2_X_REG) Register Address Description Reset Value COORD2_ X_REG 0x4D408324 Coordinate_2 X Register...
Page 447 S3C2451X RISC MICROPROCESSOR Range: 0 ~ 2039 Reserved [15:11] [10:0] Coordinate_3 X Range: 0 ~ 2039 COORDINATE_3 X REGISTER (COORD3_X_REG) Register Address Description Reset Value COORD3_ X_REG 0x4D408334 Coordinate_3 X Register Field Description Initial State Reserved [31:11] COORD3_X [10:0] Coordinate_3 X...
Page 448 S3C2451X RISC MICROPROCESSOR Rotation ROTATION ORIGIN COORDINATE REGISTER (ROT_OC_REG) Register Address Description Reset Value ROT_OC_REG 0x4D408340 Rotation Origin Coordinate Register Field Description Initial State Reserved [31:27] [26:16] X coordinate of the reference point of rotation Range: 0 ~ 2039 Reserved...
Page 449 S3C2451X RISC MICROPROCESSOR Field Description Initial State Reserved [31:6] Y-flip X-flip 270° Rotation 180° Rotation 90° Rotation 0° Rotation * If the two or more of Rn are set to 1 at the same time, drawing engine operates unpredictably. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 450 S3C2451X RISC MICROPROCESSOR X,Y Increment Setting X INCREMENT REGISTER (X_INCR_REG) Register Address Description Reset Value X_INCR_REG 0x4D408400 X Increment Register Field Description Initial State Reserved [31:22] X_INCR [21:0] X increment value (2’s complement, 11-digit fraction) Y INCREMENT REGISTER (Y_INCR_REG) Register...
Page 451 S3C2451X RISC MICROPROCESSOR ROP & Alpha Setting RASTER OPERATION REGISTER (ROP_REG) Register Address Description Reset Value ROP_REG 0x4D408410 Raster Operation Register Field Description Initial State Reserved [31:14] [13] Third Operand Select : 1’b0 : Pattern 1’b1 : Foreground Color [12:10] Alpha Mode : 3’b000 : No Alpha Blending...
Page 452 S3C2451X RISC MICROPROCESSOR Color FOREGROUND COLOR REGISTER (FG_COLOR_REG) Register Address Description Reset Value FG_COLOR_REG 0x4D408500 Foreground Color Register Field Description Initial State ForegroundColor [31:0] Foreground Color Value. The alpha field of the foreground color will be discarded. BACKROUND COLOR REGISTER (BG_COLOR_REG)
Page 453 S3C2451X RISC MICROPROCESSOR Narrow 1: YUV narrow range (Y:16-235, UV: 16-240) 0: YUV wide range (YUV: 0-255) 1: YUV mode 0: RGB mode This bit should be set to 0 in point/line drawing mode and color expansion mode. 3’b000: RGB_565...
Page 454 S3C2451X RISC MICROPROCESSOR Pattern PATTERN REGISTER (PAT_REG) Register Address Description Reset Value PAT_REG 0x4D408600 Pattern Register ~ 67C Field Description Initial State PAT_REG [31:0] Pattern Register PATTERN OFFSET REGISTER (PATOFF_REG) Register Address Description Reset Value PATOFF_REG 0x4D408700 Pattern Offset Register...
Page 455 S3C2451X RISC MICROPROCESSOR Stencil Test COLORKEY CONTROL REGISTER (COLORKEY_CTRL_REG) Register Address Description Reset Value COLORKEY_CTRL 0x4D408720 Colorkey Control Register _REG Field Description Initial State Reserved [31:5] StencilInverse 0: Normal stencil test 1 : Inversed stencil test This bit should be set to 0 if the stencil test of every color field is disabled.
Page 456 S3C2451X RISC MICROPROCESSOR Field Description Initial State A_DR(max) [31:24] Alpha DR MAX value R_DR(max) [23:16] RED DR MAX value G_DR(max) [15:8] GREEN DR MAX value B_DR(max) [7:0] BLUE DR MAX value Image Base Address SOURCE IMAGE BASE ADDRESS REGISTER (SRC_BASE_ADDR_REG)
Page 457 S3C2451X RISC MICROPROCESSOR HS_SPI CONTROLLER HS_SPI CONTROLLER OVERVIEW The High Speed Serial Peripheral Interface (HS_SPI) can interface the serial data transfer. HS_SPI has two 8/16/32-bit shift registers for transmission and receiving, respectively. During an HS_SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). HS_SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface.
Page 458 The HS_SPI in S3C2451x transfers 1-bit serial data between S3C2451x and external device. The HS_SPI in S3C2451x supports that CPU or DMA can access to transmit or receive FIFOs separately and to transfer data in both direction simultaneously. HS_SPI has 2 channel, TX channel and RX channel. TX channel has a path only from Tx FIFO to external device.
Page 459 FIFO ACCESS The HS_SPI in S3C2451x supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs can be selected 8-bit/16-bit/32-bit data. If 8-bit data size is chosen, valid bits are from 0 bit to 7 bit.
Page 460 HS_SPI CONTROLLER S3C2451X RISC MICROPROCESSOR HS_SPI TRANSFER FORMAT The S3C2451X supports 4 different format to transfer the data. Figure 29-1 shows four waveforms for HS_SPICLK.. CPOL = 0, CPHA = 0 (Format A) Cycle SPICLK MOSI MISO *MSB *MSB : MSB of previous frame...
Page 461 S3C2451X RISC MICROPROCESSOR HS_SPI CONTROLLER SPECIAL FUNCTION REGISTER DESCRIPTIONS SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER Special Function Register should be set as the following sequence. (nCS manual mode) 1. Set Transfer Type. ( CPOL & CPHA set ) 2. Set Clock configuration register.
Page 462 HS_SPI CONTROLLER S3C2451X RISC MICROPROCESSOR R/W HS_SPI Rx Channel On RxChOn 1’b0 0: Channel Off 1: Channel On R/W HS_SPI Tx Channel On TxChOn 1’b0 0: Channel Off 1: Channel On Register Address Description Reset Value Clk_CFG(Ch0) 0x52000004 Clock configuration register...
Page 463 S3C2451X RISC MICROPROCESSOR HS_SPI CONTROLLER Rx FIFO trigger level in INT mode. RxTrigger [16:11] 6’b0 Trigger level is from 0 to 63. The value means byte number in RX FIFO TxTrigger [10:5] Tx FIFO trigger level in INT mode 6’b0 Trigger level is from 0 to 63.
Page 464 HS_SPI CONTROLLER S3C2451X RISC MICROPROCESSOR HS_SPI_INT_EN Description Initial State Interrupt Enable for trailing count to be zero IntEnTrailing 1’b0 0: Disable 1:Enable Interrupt Enable for RxOverrun IntEnRxOverrun 1’b0 0: Disable 1:Enable Interrupt Enable for RxUnderrun IntEnRxUnderrun 1’b0 0: Disable 1:Enable...
Page 465 S3C2451X RISC MICROPROCESSOR HS_SPI CONTROLLER 0 ~ 7’h40 byte Rx Fifo overrun error RxOverrun 1’b0 0: no error, 1: overrun error Rx Fifo underrun error RxUnderrun 1’b0 0: no error, 1: underrun error Tx Fifo overrun error TxOverrun 1’b0 0: no error,...
Page 466 HS_SPI CONTROLLER S3C2451X RISC MICROPROCESSOR the HS_SPI channel. Register Address Description Reset Value Packet_Count_reg(Ch0) 0x52000020 R/W Count how many data master gets Packet_Count_reg(Ch1) 0x59000020 R/W Count how many data master gets Packet_Count_reg Description Initial State Enable bit for packet count...
Page 467 S3C2451X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address Description Reset Value Pending_clr_reg(Ch0) 0x52000024 R/W Pending clear register Pending_clr_reg(Ch1) 0x59000024 R/W Pending clear register Status_Pending Description Initial State _clear_reg TX underrun pending clear bit TX_underrun_clr 1’b0 0: non-clear 1:clear TX overrun pending clear bit TX_overrun_clr 1’b0...
Page 468 HS_SPI CONTROLLER S3C2451X RISC MICROPROCESSOR Swap enable TX_SWAP_en 1’b0 0 : normal 1 : swap ** Data size must be larger than swap size. Register Address Description Reset Value FB_Clk_sel (Ch0) 0x5200002C R/W Feedback clock selecting register. FB_Clk_sel (Ch1) 0x5900002C R/W Feedback clock selecting register.
Page 469 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER SD/MMC HOST CONTROLLER This chapter describes the SD/SDIO/MMC/CE-ATA host controller and related registers supported by S3C2451X RISC microprocessor. OVERVIEW The HSMMC (High-speed MMC) SDMMC is a combo host for Secure Digital card and MultiMedia Card. This host is compatible for SD Association’s (SDA) Host Standard Specification.
Page 470 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR BLOCK DIAGRAM HCLK SDCLK Domain Domain BaseCLK Status Clock Control INTREQ Status CMDRS System D A RG P packet (AHB) Control Control Control FIFO AHB slave I/F Control Control DPSRA Status controller DATA AHB master...
Page 471 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER SEQUENCE This section defines basic sequence flow chart divided into several sub sequences. “Wait for interrupts” is used in the flow chart. This means the Host Driver waits until specified interrupts are asserted. If already asserted, then fall through that step in the flow chart.
Page 472 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR SD CLOCK SUPPLY SEQUENCE START Calculate a divisor for SD Clock frequency Set SDCLK frequency select and Internal Clock Enable Check Internal Clock Enable Set SD Clock ON Figure 21-3SD Clock Supply Sequence The sequence for supplying SD Clock to a SD card is described in Figure 21-3. The clock shall be supplied to the card before either of the following actions is taken.
Page 473 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER SD CLOCK STOP SEQUENCE START Set SD Clock OFF Stop SD Clock Figure 21-4SD Clock Stop Sequence The flow chart for stopping the SD Clock is shown in Figure 21-4. The Host Driver shall not stop the SD Clock when a SD transaction is occurring on the SD Bus -- namely, when either Command Inhibit (DAT) or Command Inhibit (CMD) in the Present State register is set to 1.
Page 474 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR SD BUS POWER CONTROL SEQUENCE START Get the support voltage of the Host Controller Set SD Bus voltage select with supported maximum voltage Set SD Bus Power Get OCR value of the SD Card no change...
Page 475 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER CHANGE BUS WIDTH SEQUENCE START Disable Card Interrupt in Host SD Memory Only Card ? SD Memory Only Card ? Mask Card Interrupt in Card Enable Card Interrupt in Card Change Bit Mode in Card...
Page 476 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR TIMEOUT SETTING FOR DAT LINE START Calculate a Divisor for detecting Timeout Set Timeout Detection Timer Figure 21-8 Timeout Setting Sequence In order to detect timeout errors on DAT line, the Host Driver shall execute the following two steps before any SD transaction.
Page 477 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER SD COMMAND ISSUE SEQUENCE Figure 21-9 Timeout Setting Sequence (1) Check Command Inhibit (CMD) in the Present State register. Repeat this step until Command Inhibit (CMD) is 0. That is, when Command Inhibit (CMD) is 1, the Host Driver shall not issue a SD Command.
Page 478 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR (4) Check Command Inhibit (DAT) in the Present State register. Repeat this step until Command Inhibit (DAT) is (5) Set the value corresponding to the issued command in the Argument register. (6) Set the value corresponding to the issued command in the Command register.
Page 479 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER START Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Command with Transfer Complete Int ? Wait for Transfer Complete Int Transfer Complete Int occur Clr Transfer Complete Status...
Page 480 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR TRANSACTION CONTROL WITH DATA TRANSFER USING DAT LINE Depending on whether DMA (optional) is used or not, there are two execution methods. The sequence not using DMA is shown in Figure 21-11 and the sequence using DMA is shown in Figure 21-12.
Page 481 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER START Set Block Size Reg Set Command Reg Wait for Command Set Block Count Reg Complete Int Command Complete Int occur Set Argument Reg Clr Command Complete Status Set Transfer Mode Reg Get Response Data...
Page 482 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR (1) Set the value corresponding to the executed data byte length of one block to Block Size register. (2) Set the value corresponding to the executed data block count to Block Count Register. (3) Set the value corresponding to the issued command to Argument register.
Page 483 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER START Set System Address Reg (10) Set Block Size Reg Wait for Transfer Complete Int and DMA Int Set Block Count Reg Transfer Complete Int (11) occur Check Interrupt Status Set Argument Reg DMA Int occur...
Page 484 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR (7) And then wait for the Command Complete Interrupt. (8) Write 1 to the Command Complete(STACMDCMPLT) in the Normal Interrupt Status register to clear this bit. (9) Read Response register and get necessary information in accordance with the issued command.
Page 485 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER SDI SPECIAL REGISTERS CONFIGURATION REGISTER TYPES Configuration register fields are assigned one of the attributes described below : Register Description Attribute Read-only register: Register bits are read-only and cannot be altered by software or any reset operation.
Page 486 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR SDMA SYSTEM ADDRESS REGISTER Register Address Description Reset Value SYSAD0 0X4AC00000 System Address register (Channel 0) SYSAD1 0X4A800000 System Address register (Channel 1) This register contains the physical system memory address used for DMA transfers.
Page 487 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER BLOCK SIZE REGISTER This register is used to configure the number of bytes in a data block. Register Address Description Reset Value BLKSIZE0 0X4AC00004 Host DMA Buffer Boundary and Transfer Block Size Register (Channel 0)
Page 488 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR 0000h = No data transfer BLOCK COUNT REGISTER This register is used to configure the number of data blocks. Register Address Description Reset Value BLKCNT0 0X4AC00006 Blocks Count For Current Transfer (Channel 0) BLKCNT1 0X4A800006...
Page 489 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER ARGUMENT REGISTER This register contains the SD Command Argument. Register Address Description Reset Value ARGUMENT0 0X4AC00008 Command Argument Register (Channel 0) ARGUMENT1 0X4A800008 Command Argument Register (Channel 1) Name Description Initial Value ARGUM [31:0] Command Argument The SD Command Argument is specified as bit39-8 of Command- Format in the SD Memory Card Physical Layer Specification.
Page 490 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR TRANSFER MODE REGISTER This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (see Data Present Select in the Command register), or before issuing a Resume command.
Page 491 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER Block Count Enable ENBLKC This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer. (Refer to the Table below ”Determination of Transfer Type”...
Page 492 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR COMMAND REGISTER This register contains the SD Command Argument. Register Address Description Reset Value CMDREG0 0X4AC0000E Command Register (Channel 0) CMDREG1 0X4A80000E Command Register (Channel 1) The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State register before writing to this register.
Page 493 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER DATAPR Data Present Select This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: (1) Commands using only CMD line (ex. CMD52).
Page 494 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR RESPONSE REGISTER This register is used to store responses from SD cards. Register Address Description Reset Value RSPREG0_0 0X4AC00010 Response Register 0 (Channel 0) RSPREG1_0 0X4AC00014 Response Register 1 (Channel 0) RSPREG2_0 0X4AC00018 Response Register 2 (Channel 0)
Page 495 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER 32-bit bus system. Parts of the response, the Index field and the CRC, are checked by the Host Controller (as specified by the Command Index Check Enable and the Command CRC Check Enable bits in the Command register) and generate an error interrupt if an error is detected.
Page 496 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR BUFFER DATA PORT REGISTER 32-bit data port register to access internal buffer. Register Address Description Reset Value BDATA0 0X4AC00020 Buffer Data Register (Channel 0) BDATA1 0X4A800020 Buffer Data Register (Channel 1) Name Description Initial Value...
Page 497 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER PRESENT STATE REGISTER This register contains the SD Command Argument. Register Address Description Reset Value PRNSTS0 0X4AC00024 RO/ROC Present State Register (Channel 0) 0x000A0000 RO/ROC Present State Register (Channel 1) PRNSTS1 0X4A800024 0x000A0000 Name Description...
Page 498 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR Status register and changing from 1 to 0 generates a Card Removal interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register shall not affect this bit. If a card is removed while its power is on and its clock is oscillating, the Host Controller shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock Control register.
Page 499 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER Read Transfer Active (ROC) RDTR This status is used for detecting completion of a read transfer. ANAC This bit is set to 1 for either of the following conditions: (1) After the end bit of the read command.
Page 500 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR (1) When the end bit of the last data block is sent from the SD Bus to the Host Controller. (2) When beginning a wait read transfer at a stop at the block gap initiated by a Stop At Block Gap Request.
Page 501 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER Stable SDCD=1 Card Inserted Power ON Reset Debouncing Once debouncing clock becomes valid Stable No Card SDCD=0 Figure 21-13 Card Detect State The above Figure shows the state definitions of hardware that handles “Debouncing”. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 502 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR Figure 21-14Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer Figure 21-15 Timing of Command Inhibit (DAT) for the case of response with busy Figure 21-16 Timing of Command Inhibit (CMD) for the case of no response command Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 503 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER HOST CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value HOSTCTL0 0X4AC00028 Present State Register (Channel 0) HOSTCTL1 0X4A800028 Present State Register (Channel 1) Name Description Initial Value Reserved CDSI...
Page 504 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR POWER CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value PWRCON0 0X4AC00029 Present State Register (Channel 0) PWRCON1 0X4A800029 Present State Register (Channel 1) Name Description Initial Value [7:4] Reserved...
Page 505 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER BLOCK GAP CONTROL REGISTER This register contains the SD Command Argument. Register Address Description Reset Value BLKGAP0 0X4AC0002A Block Gap Control Register (Channel BLKGAP1 0X4A80002A Block Gap Control Register (Channel Name Description Initial Value [7:4]...
Page 506 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR block gap. The Host Controller shall honor Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the Host Driver shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1.
Page 507 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER WAKEUP CONTROL REGISTER This register is mandatory for the Host Controller, but wakeup functionality depends on the Host Controller system hardware and software. The Host Driver shall maintain voltage on the SD Bus, by setting SD Bus Power to 1 in the Power Control register, when wakeup event via Card Interrupt is desired.
Page 508 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR CLOCK CONTROL REGISTER At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select according to the Capabilities register. Register Address Description Reset Value CLKCON0 0X4AC0002C Command Register (Channel 0)
Page 509 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER start until this bit is set to 1. (ROC) ‘1’ = Ready ‘0’ = Not Ready ENSDCL SD Clock Enable The Host Controller shall stop SDCLK when writing this bit to 0. SDCLK Frequency Select can be changed when this bit is 0. Then, the Host Controller shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK=0).
Page 510 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR TIMEOUT CONTROL REGISTER At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value according to the Capabilities register. Register Address Description Reset Value TIMEOUTCON 0 0X4AC0002E Timeout Control Register (Channel 0)
Page 511 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt Block Gap Event Transfer Complete ‘1’ = Reset ‘0’ = Work Software Reset For CMD Line RSTCMD Only part of command circuit is reset.
Page 512 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR NORMAL INTERRUPT STATUS REGISTER The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not affect these reads. An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1.
Page 513 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER to the Host System. It is necessary to define how to handle this delay. When this status has been set and the Host Driver needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt...
Page 514 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR This bit is set at the falling edge of Write Transfer Active Status (After getting CRC status at SD Bus timing). ‘1’ = Transaction stopped at block gap ‘0’ = No Block Gap Event Transfer Complete STATRANC This bit is set when a read / write transfer is completed.
Page 515 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER ERROR INTERRUPT STATUS REGISTER Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but not by the Error Interrupt Signal Enable register. The interrupt is generated when the Error Interrupt Signal Enable is enabled and at least one of the statuses is set to 1.
Page 516 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR (2) Busy timeout after Write CRC status (3) Write CRC Status timeout (4) Read Data timeout. ‘1’ = Timeout ‘0’ = No Error Command Index Error STACMD Occurs if a Command Index error occurs in the command response.
Page 517 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER NORMAL INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Interrupt Status. Register Address Description Reset Value NORINTSTSEN0 0X4AC00034 Normal Interrupt Status Enable Register (Channel 0) NORINTSTSEN1 0X4A800034 Normal Interrupt Status Enable Register (Channel 1) Name...
Page 518 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR Buffer Read Ready Status Enable ENSTABUFR ‘1’ = Enabled DRDY ‘0’ = Masked Buffer Write Ready Status Enable ENSTABUF ‘1’ = Enabled WTRDY ‘0’ = Masked DMA Interrupt Status Enable ‘1’ = Enabled ENSTADMA ‘0’ = Masked...
Page 519 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER ERROR INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Error Interrupt Status. Register Address Description Reset Value ERRINTSTSEN0 0X4AC00036 Error Interrupt Status Enable Register (Channel 0) ERRINTSTSEN1 0X4A800036 Error Interrupt Status Enable Register (Channel 1)
Page 520 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR NORMAL INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status bits all share the same1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
Page 521 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER Buffer Write Ready Signal Enable ENSIGBUFW ‘1’ = Enabled TRDY ‘0’ = Masked DMA Interrupt Signal Enable ‘1’ = Enabled ENSIGDMA ‘0’ = Masked Block Gap Event Signal Enable ENSIGBLKG ‘1’ = Enabled ‘0’ = Masked...
Page 522 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR ERROR INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is notified to the Host System as the interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
Page 523 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER AUTOCMD12 ERROR STATUS REGISTER When Auto CMD12 Error Status is set, the Host Driver shall check this register to identify what kind of error Auto CMD12 indicated. This register is valid only when the Auto CMD12 Error is set.
Page 524 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR Auto CMD12 CRC Auto CMD12 Kinds of error Error Timeout Error No Error Response Timeout Error Response CRC Error CMD line conflict The relation between Command CRC Error and Command Timeout Error The timing of changing Auto CMD12 Error Status can be classified in three scenarios: (1) When the Host Controller is going to issue Auto CMD12 Set D00 to 1 if Auto CMD12 cannot be issued due to an error in the previous command.
Page 525 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER CAPABILITIES REGISTER This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control.
Page 526 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR Base Clock Frequency For SD Clock (HWInit) This value indicates the base (maximum) clock frequency for the SD Clock. Unit values are 1MHz. If the real frequency is 16.5MHz, the lager value shall be set 01 0001b (17MHz) because the Host Driver use this...
Page 527 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER MAXIMUM CURRENT CAPABILITIES REGISTER These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the Capabilities register. If this information is supplied by the Host System via another method, all Maximum Current Capabilities register shall be 0.
Page 528 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR CONTROL REGISTER 2 Register Address Description Reset Value CONTROL2_0 0X4AC00080 Control register 2 (Channel 0) CONTROL2_1 0X4A800080 Control register 2 (Channel 1) Initial Name Description Value [31] Write Status Clear Async Mode Enable This bit can make async-clear enable about Normal and Error interrupt status bit.
Page 529 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER CDSYNCSEL [12] SD Card Detect Sync Support This field is used to enable output CMD and DAT referencing SD Bus Power bit in the “PWRCON register”, when being set. ‘0’=No Sync, no switch output enable signal (Command, Data) ‘1’=Sync, control output enable signal (Command, Data)
Page 530 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR Note : Ensure to always set SDCLK Hold Enable (EnSCHold) if the card does not support Read Wait to guarantee for Receive data not overwritten to the internal FIFO memory. Note : CMD_wo_DAT issue is prohibited during READ transfer when SDCLK Hold Enable is set Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 531 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER CONTROL REGISTER 3 Register Address Description Reset Value FIFO Interrupt Control (Control Register 3) CONTROL3_0 0X4AC00084 0x7F5F3F1F (Channel 0) FIFO Interrupt Control (Control Register 3) CONTROL3_1 0X4A800084 0x7F5F3F1F (Channel 1) Name Description Initial Value FCSEL3...
Page 532 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR DEBUG REGISTER Register Address Description Reset Value DEBUG_0 0X4AC00088 DEBUG register (Channel Not fixed DEBUG_1 0X4A800088 DEBUG register (Channel Not fixed Initial Name Description Value DBGREG [31:0] Debug Register fixed Read Only Register for Debug Purpose (RO)
Page 533 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER FORCE EVENT REGISTER FOR AUTO CMD12 ERROR STATUS Register Address Description Reset Value FEAER0 0X4AC00050 Force Event Auto CMD12 Error Interrupt 0x0000 Register Error Interrupt (Channel 0) FEAER1 0X4A800050 Force Event Auto CMD12 Error Interrupt...
Page 534 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR FORCE EVENT REGISTER FOR ERROR INTERRUPT STATUS Register Address Description Reset Value FEERR0 0X4AC00052 Force Event Error Interrupt Register 0x0000 Error Interrupt (Channel 0) FEERR1 0X4A800052 Force Event Error Interrupt Register 0x0000 Error Interrupt (Channel 1) The Force Event Register is not a physically implemented register.
Page 535 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER Force Event for Command Timeout Error 1=Interrupt is generated 0=No Interrupt Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 21-67 Specifications and information herein are subject to change without notice.
Page 536 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR ADMA ERROR STATUS REGISTER When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the...
Page 537 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER ‘1’= Error ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state. [1:0] D01 – D00 ADMA Error State when error is occurred Contents of SYS_SDR register ‘00’...
Page 538 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR ADMA System Address Register This register contains the physical Descriptor address used for ADMA data transfer. Register Address Description Reset Value ADMASYSADDR0 0X4AC00058 ADMA System Address Register (Channel 0) 0x00 ADMASYSADDR1 0X4A800058 ADMA System Address Register (Channel 1)
Page 539 S3C2451X RISC MICROPROCESSOR HSMMC CONTROLLER HOST CONTROLLER VERSION REGISTER Register Address Description Reset Value HCVER0 0X4AC000FE HWInit Host Controller Version Register (Channel 0x0401 HCVER1 0X4A8000FE HWInit Host Controller Version Register (Channel 0x0401 Name Description Initial Value Vendor Version Number This status is reserved for the vendor version number. The Host Driver...
Page 540 HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR NOTES Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 21-72 Specifications and information herein are subject to change without notice.
Page 541 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER OVERVIEW The LCD controller consists of logic for transferring image data from a video buffer located in system memory to an external LCD driver interface. LCD driver interface has two kind of interface. One is conventional RGB- interface and the other is i80-System interface.
Page 542 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR FEATURES The features of LCD controller are: • Bus Interface 32-bit AMBA AHB Master /AHB Slave • Video Output Interface RGB Parallel I/F (24-bit) RGB Serial I/F (8-bit) i80-System I/F (18-bit) • PIP (OSD) function...
Page 543 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER FUNCTIONAL DESCRIPTION BRIEF OF THE SUB-BLOCK The LCD controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR has 71 programmable register sets and two-256x25 palette memory, which are used to configure the LCD controller. The VDMA is a dedicated LCD DMA, which it can transfer the video data in frame memory to VPRCS.
Page 544 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR AMBA Win0(RGB) Win1(RGB) Blending Color key OUTPUT(RGB) Figure 22-2. Block diagram of the Data Flow INTERFACE LCD controller supports 2 types of display device. One type is the conventional RGB-interface that uses RGB data, Vertical/horizontal sync, data valid signal and data sync clock. The Second type is i80-System interface that uses address, data, chip select, read/write control and register/status indicating signal.
Page 545 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER OVERVIEW OF THE COLOR DATA RGB Data format The LCD controller requests the specified memory format of frame buffer. The next table shows some examples of each display mode. 28BPP display (A4+888) (BSWP = 0, HWSWP = 0, BLD_PIX = 1, ALPHA_SEL = 1)
Page 546 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR 25BPP display (A888) (BSWP = 0, HWSWP = 0) D[31:25] D[24] D[23:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTE: AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied.
Page 547 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER 24BPP display (A887) (BSWP = 0, HWSWP = 0) D[31:24] D[23] D[22:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTE: AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied.
Page 548 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR 24BPP display (888) (BSWP = 0, HWSWP = 0) D[31:24] D[23:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTE: D[23:16] = Red data, D[15:8] = Green data, D[7:0] = Blue data Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 549 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER 19BPP display (A666) (BSWP = 0, HWSWP = 0) D[31:19] D[18] D[17:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel NOTE: AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied.
Page 550 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR 18BPP display (666) (BSWP = 0, HWSWP = 0) D[31:18] D[17:0] 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit ..LCD Panel ..LCD Panel NOTE: D[17:12] = Red data, D[11:6] = Green data, D[5:0] = Blue data Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 551 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER 16BPP display (A555) (BSWP = 0, HWSWP = 0) D[31] D[30:16] D[15] D[14:0] 000H AEN1 AEN2 004H AEN3 AEN4 008H AEN5 AEN6 (BSWP = 0, HWSWP = 1) [31] D[30:16] D[15] D[14:0] 000H AEN2 AEN1...
Page 552 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR 16BPP display (1+555) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H NOTE: {D[14:10], D[15] } = Red data, {D[9:5], D[15] } = Green data, {D[4:0], D[15]}= Blue data Figure 22-3.
Page 553 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER 16BPP display (565) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H 004H 008H (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H 004H 008H NOTE: D[15:11] = Red data, D[10:5] = Green data, D[4:0] = Blue data Figure 22-4.
Page 554 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR 8BPP display (A232) (BSWP = 0, HWSWP = 0) D[31] D[30:24] D[23] D[22:16] D[15] D[14:8] D[7] D[6:0] 000H AEN1 AEN2 AEN3 AEN4 004H AEN5 AEN6 AEN7 AEN8 008H AEN9 AEN10 AEN11 AEN12 (BSWP = 1, HWSWP = 0)
Page 555 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER 8BPP display (Palette) (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H 004H 008H ..LCD Panel NOTE: The values of frame buffer are index of palette memory.
Page 556 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR 4BPP display (Palette) (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H 004H 008H (BSWP = 1, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H...
Page 557 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER 2BPP display (Palette) (BSWP = 0, HWSWP = 0) [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 002H 006H 00AH … [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000H 004H 008H 1BPP display (Palette)
Page 558 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR VD SIGNAL CONNECTION VD Pin Descriptions at 24BPP RGB parallel 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GREEN BLUE VD Pin Descriptions at 18BPP RGB parallel 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 559 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER VD Pin Descriptions at 18BPP i80-System Interface 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GREEN BLUE VD Pin Descriptions at 16BPP i80-System Interface 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 560 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR PALETTE USAGE Palette Configuration and Format Control The LCD controller can support the 256 colors palette for various selection of color mapping. The user can select 256 colors from the 24-bit colors through these four formats.
Page 561 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Table 22-2. 19BPP (A:6:6:6) Palette Data Format INDEX\Bit Pos. … ..… … … … … … … … … … … … … … … … … … Number of Table 22-3. 16BPP(A:5:5:5) Palette Data Format INDEX\Bit Pos.
Page 562 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR WINDOW BLENDING OVERVIEW The main function of the VPRCS module is window blending. LCD controller has 2-window layers and the detail is described below. As an example of application, System can use win0 as an OS window, full TV screen window or etc.
Page 563 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER BLENDING DIAGRAM/DETAILS LCD controller could blend 2-Layer for the only one pixel at the same time. The Blending factor, alpha value is controlled by ALPHA0_R/G/B and ALPHA1_R/G/B fields in Window 1 Alpha Value register or DATA[27:24] in frame buffer, which are implemented for each window layer and color(R,G,B).
Page 564 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR COMPKEY Mask bit of COLVAL to compare with Window color DIRCON COLVAL Frame Buffer Compare R’G’B’ Window0 (Background) Selected Window Match with COLVAL : Window1 Unselected window (Foreground) Unmatched with CONVAL : Selected window Figure 22-6. Color Key Block Diagram...
Page 565 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER OSD Image 180x100 Back-Ground 320x240 Blended (Alpha = 0x9) Blended (Alpha = 0xf) and No Color key and No Color key No Blend and Blended (Alpha = 0x0) Color Key Enable Blended (Alpha = 0x9) and Color Key Enable Figure 22-8.
Page 566 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR VTIME CONTROLLER OPERATION RGB INTERFACE The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2 registers in the VSFR register. Base on these programmable configurations of the display control registers in VSFR, the VTIME module can generate the programmable control signals suitable for the support of many different types of display device.
Page 567 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY The LCD controller supports the hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL registers need to be changed (refer to Figure 22-9), but PAGEWIDTH and OFFSIZE value do not change.
Page 568 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR RGB INTERFACE I/O Signals Name Type Description RGB_HSYNC Output Horizontal Sync. Signal RGB_VSYNC Output Vertical Sync. Signal RGB_VCLK Output LCD Video Clock RGB_VDEN Output Data Enable RGB_VD[23:0] Output RGB data output RGB I/F Timing 1 FRAME...
Page 569 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER LCD CPU INTERFACE I/O (i80-SYSTEM I/F) Signals Name Type Description SYS_VD[17:0] InOut Video Data SYS_CS0 Output Chip select for Main LCD SYS_CS1 Output Chip select for Sub LCD SYS_WR Output Write enable SYS_OE Output Output enable...
Page 570 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR LCD SIGNAL MUXING Table 22-6. LCD Signal Muxing Table (RGB and i-80 I/F) VIDOUT Signals 10/11 SYS_WR RGB_VCLK/SYS_WR Reserved RGB_VCLK 10/11 SYS_CS0 RGB_HSYNC/SYS_CS0 Reserved RGB_HSYNC 10/11 SYS_CS1 RGB_VSYNC/SYS_CS1 Reserved RGB_VSYNC 10/11 SYS_RS RGB_VDEN/SYS_RS Reserved RGB_VDEN...
Page 571 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER PROGRAMMER’S MODEL OVERVIEW The following registers are used to configure LCD controller 1. VIDCON0: Configure Video output format and display enable/disable. 2. VIDCON1: RGB I/F control signal. 3. SYSIFCONx: i80-System I/F control signal. 4. VIDTCONx: Configure Video output Timing and determine the size of display.
Page 572 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Register Descriptions (Continued) Register Address Description Reset Value VIDW00ADD0B0 0x4C800064 R/W Window 0’s buffer start address register, buffer 0 0x0000_0000 VIDW00ADD0B1 0x4C800068 R/W Window 0’s buffer start address register, buffer 1 0x0000_0000 VIDW01ADD0 0x4C80006C R/W Window 1’s buffer start address register...
Page 573 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Video Main Control 0 Register Register Address Description Reset Value VIDCON0 0x4C800000 Video control 1 register 0x0000_0000 VIDCON0 Description Initial State Reserved [31:24] Reserved 0x00 VIDOUT [23:22] It determines the output format of LCD Controller...
Page 574 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Video Main Control 0 Register (Continued) VIDCON0 Description Initial State CLKVALUP [12] Select CLKVAL_F Update timing control 0 = Always 1 = Start of a frame (Only once per frame) CLKVAL_F [11:6] Determine the rates of VCLK.
Page 575 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Video Main Control 1 Register Register Address Description Reset Value VIDCON1 0x4C800004 Video control 2 register 0x0000_0000 VIDCON1 Description Initial state LINECNT [26:16] Provide the status of the line counter (read only) (read only) Up count from 0 to LINEVAL...
Page 576 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Video Time Control 1 Register Register Address Description Reset Value VIDTCON1 0x4C80000C Video time control 2 register 0x0000_0000 VIDTCON1 Description Initial state HBPD [23:16] Horizontal back porch is the number of VCLK periods between 0000000 the edge of HSYNC and the start of active data.
Page 577 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Window 0 Control Register Register Address Description Reset Value WINCON0 0x4C800014 Window 0 control register 0x0000_0000 WINCON0 Description Initial State Status of Current display Buffer (Read only) 0 = buffer0 display 1 = buffer1 display...
Page 578 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Window 0 Control Register (Continued) WINCON0 Description Initial State Reserved Reserved ENWIN_F Window0 on/ off control 0 = Off window0. 1 = On window0. Window 1 Control Register Register Address Description Reset Value WINCON1 0x4C800018...
Page 579 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Window 1 Control Register (Continued) WINCON1 Description Initial State ALPHA_SEL Alpha value selection Per plane blending case( BLD_PIX ==0) 0 = using ALPHA0_R/G/B values 1 = using ALPHA1_R/G/B values Per pixel blending case( BLD_PIX ==1)
Page 580 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Window 1 Position Control A Register Register Address Description Reset Value VIDOSD1A 0x4C800034 Video Window 1’s position control 2 register 0x0000_0000 VIDOSD1A Description initial state OSD_LeftTopX_F [21:11] Horizontal screen coordinate for left top pixel of OSD image...
Page 581 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER FRAME Buffer Address 0 Register Register Address Description Reset Value VIDW00ADD0B0 0x4C800064 0x0000_0000 Window 0’s buffer start address register, buffer 0 VIDW00ADD0B1 0x4C800068 0x0000_0000 Window 0’s buffer start address register, buffer 1 VIDW01ADD0 0x4C80006C 0x0000_0000 Window 1’s buffer start address register...
Page 582 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR FRAME Buffer Address 2 Register(Virtual screen) Register Address Description Reset Value VIDW00ADD2B0 0x4C800094 0x0000_0000 Window 0’s buffer size register, buffer 0 VIDW00ADD2B1 0x4C800098 0x0000_0000 Window 0’s buffer size register, buffer 1 VIDW01ADD2 0x4C80009C 0x0000_0000 Window 1’s buffer size register...
Page 583 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER VIDEO interrupt Control Register Register Address Description Reset Value VIDINTCON 0x4C8000AC Indicate the Video interrupt control register 0x3F00000 VIDINTCON Description Initial state FIFOINTERVAL [25:20] These bits control the interval of the FIFO interrupt. 0x3F SYSMAINCON...
Page 584 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Win1 Color Key 0 Register Register Address Description Reset Value W1KEYCON0 0x4C8000B0 Color key control register 0x0000_0000 W1KEYCON0 Description Initial state KEYBLEN [26] Alpha value control for Key area or Non-Key area 0 = Alpha value selected by AEN bit in frame buffer...
Page 585 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER WIN 1 Color key 1 Register Register Address Description Reset Value W1KEYCON1 0x4C8000B4 Color key value ( transparent value) register 0x0000_0000 W1KEYCON1 Description Initial state COLVAL [23:0] Color key value for the transparent pixel effect Note: COLVAL and COMPKEY use 24-bit color data at all bpp mode.
Page 586 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR WIN0 Color MAP Register Address Description Reset Value WIN0MAP 0x4C8000D0 Window color control 0x0000_0000 WIN0MAP Description Initial state MAPCOLEN_F [24] Window’s color mapping control bit. If this bit is enabled then Video DMA will stop, and MAPCOLOR will be appear on back-ground image instead of original image.
Page 587 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Window Palette control Register Register Address Description Reset Value WPALCON 0x4C8000E4 Window Palette control register 0x0000_0000 WPALCON Description Initial state PALUPDATEEN Palette memory access-right control bit. Users should set this bit before access (write or read) palette memory, in this case LCD controller cannot access palette.
Page 588 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR Main LCD i80-System Interface control Register Address Description Reset Value SYSIFCON0 0x4C800130 i80-System Interface control for Main LDI(LCD) 0x0000_0000 SYSIFCON1 0x4C800134 i80-System Interface control for Sub LDI(LCD) 0x0000_0000 SYSIFCONx Description Initial State Reserved [23:20] Reserved...
Page 589 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER Dithering Control 1 Register Register Address Description Reset Value DITHMODE 0x4C800138 Dithering mode register 0x0000_0000 DITHMODE Description Initial state Reserved [30:7] Not used for normal access (Write not-zero values to these register make to come out abnormal result )
Page 590 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR i80-System Interface Command Control 0 Register Address Description Reset Value SIFCCON0 0x4C80013C i80-System Interface Command Control 0x0000_0000 SIFCCON0 Description Initial State Reserved [11:10] Reserved SYS_CS0_CON LCD i80-System Interface SYS_CS0 (main) Signal control 0: Disable (High)
Page 591 S3C2451X RISC MICROPROCESSOR LCD CONTROLLER i80-System Interface Command Control 1 Register Address Description Reset Value SIFCCON1 0x4C800140 i80-System Interface Command Data Write register 0x0000_0000 SIFCCON1 Description Initial State Reserved [23:18] Reserved SYS_WDATA [17:0] LCD i80-System Interface Write Data i80-System Interface Command Control 2...
Page 592 LCD CONTROLLER S3C2451X RISC MICROPROCESSOR i80-System I/F TRIGGER CONTROL 2 Register Register Address Description Reset Value CPUTRIGCON2 0x4C800160 Software-Based Trigger control register 0x0000_0000 CPUTRIGCON2 Description Initial State SWTRIG Software-Based Transmission Trigger When this bit is set, trigger happens. This bit is automatically cleared.
Page 593 CAMERA INTERFACE OVERVIEW This specification defines the interface of camera. The CAMIF (Camera Interface) within the S3C2451X consists of eight parts. They are the pattern mux, capturing unit, MSDMA (Memory Scaling DMA), preview scaler, codec scaler, preview DMA, codec DMA, and SFR. The camera interface supports ITU R BT-601/656 YCbCr 8-bit standard and Memory.
Page 594 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR FEATURES — ITU-R BT 601/656 8-bit mode support — DZI (Digital Zoom In) capability — Programmable polarity of video sync signals — Max. 4096 x 4096 pixels input support (non-scaling) — Max. 2048 x 2048 pixels input support for codec scaling and 720 x 480 pixels input support for preview scaling —...
Page 595 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM 1 frame VSYNC Vertical lines HREF HREF (1H) Horizontal width PCLK 8-bit mode DATA[7:0] Figure 23-2. ITU-R BT 601 Input timing diagram FieldMode = 1 (Field port connects with FIELD) Field 1 Field 2...
Page 596 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR There are two timing reference signals in ITU-R BT 656 format, one at the beginning of each video data block (start of active video, SAV) and one at the end of each video data block(end of active video, EAV) as shown in Figure 23-3 and below table.
Page 597 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE EXTERNAL/INTERNAL CONNECTION GUIDE All CAMIF input signals should not occur inter-skewing to pixel clock line. CAMCLK CAMRST CAMIF No Skew VSYNC HREF Camera A PCLK PDATA[7:0] Figure 23-6. IO connection guide CAMERA INTERFACE OPERATION TWO DMA PORTS CAMIF has two DMA port.
Page 598 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR Frame Memory (SDRAM) Preview image P-port RGB 16/24 bit External Codec image Camera CAMIF YCbCr 4:2:0 ITU format Processor C-port YCbCr 4:2:2 RGB 16/24 bit Frame Memory (SDRAM) Window cut P-port Preview image RGB 16/24 bit...
Page 599 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CLOCK DOMAIN CAMIF has two clock domains. The one is the system bus clock, which is HCLK. The other is the pixel clock, which is PCLK. The system clock must be faster than pixel clock. As shown in figure 23-8, CAMCLK must be divided from the fixed frequency like USB PLL clock.
Page 600 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR 4-pingpong Frame memory (SDRAM) P-port RGB 1 P-port RGB 2 P-port RGB 3 P-port P-port RGB 4 4:4:4 ITU-601/656 YCbCr Camera AHB bus & 4:2:2 Interface Memorycontroller C-port Y 1 / RGB 1 8-bits C-port Cb 1...
Page 601 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE MEMORY STORING METHOD The storing method to the frame memory is the little-endian method in codec path. The first entering pixels stored into LSB sides, and the last entering pixels stored into MSB sides. The carried data by AHB bus is 32-bit word.
Page 602 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can be occurred in anywhere of frame period. But, it is recommend to do first setting at the VSYNC “L” state. VSYNC information can be read from status SFR. Refer to the below figure.
Page 603 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE VSYNC HREF INTERRUPT Multi frame Reserved capturing Image Capture SFR setting (ImgCptEn) < Frame Capture Start for external camera input > VSYNC HREF INTERRUPT In Capturing Image Capture Reserved New Command New SFR command < New command valid timing diagram >...
Page 604 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR Timing diagram for Last IRQ (Camera capture mode) IRQ except LastIRQ is generated before image capturing. Last IRQ which means capture-end can be set by following timing diagram. LastIRQEn is auto-cleared and ,as mentioned, SFR setting in ISR is for next frame command.
Page 605 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE region region region region region region region ENVID_MS FrameCnt ++ ImgCptEn_PrSC Preview DMA frame done (internal signal) FrameCnt Capture O Capture O Capture O Capture X Capture O Capture O (Frame_1) (Frame_3) (Frame_0) (Frame_2) (Frame_3) Figure 23-12.
Page 606 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR SOFTWARE INTERFACE CAMIF SFR (Special Function Register) CAMERA INTERFACE SPECIAL REGISTERS • When preview input use MSDMA path, the first column mark (v) sfr will be related to the preview operation. • The last column means that each value can change by each VSYNC start during capture enable.
Page 607 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE WINDOW OPTION REGISTER Register Address Description Reset Value CIWDOFST 0x4D80_0004 Window offset register SourceHsize TargetHsize_xx Original Input TargetVsize_xx Window Cut : WinHorOfst,WinHorOfst2 TargetHsize_xx TargetHsize_Co or : WinVerOfst,WinVerOfst2 TargetHsize_Pr Figure 23-14. Window offset scheme (WinHorOfst2 & WinVerOfst2 are assigned in the CIWDOFST2 register)
Page 608 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR NOTE: Clear bits should be set by zero after clearing the flags. It should be as (WinHorOfst + WinHorOfst2) >= (SourceHsize – 720 * PreHorRatio_Pr) Crop Hsize ( = SourceHsize – WinHorOfst - WinHorOfst2) must be 4’s multiple of PreHorRatio.
Page 609 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE GLOBAL CONTROL REGISTER Register Address Description Reset Value CIGCTRL 0x4D80_0008 Global control register 2000_0000 Initial Change CIGCTRL Description State State [31] Camera interface software reset. Before setting this bit, you should set the ITU601_656n bit of CISRCFMT as “1”...
Page 610 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR Overflow (preview) IRQ_Cl_p IRQ_Ovfen IRQ_p Overflow IRQ_Cl_c (codec) IRQ_c Figure 23-15 Interrupt generation scheme Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 611 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE WINDOW OPTION REGISTER 2 Register Address Description Reset Value CIDOWSFT2 0x4D80_0014 Window offset register 2 Initial Change CIWDOFST2 Description State State Reserved [31:27] [26:16] Window horizontal offset2 by pixel unit. (It should be 2’s multiple)
Page 612 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR Y3 START ADDRESS REGISTER Register Address Description Reset Value CICOYSA3 0x4D80_0020 frame start address for codec DMA Initial Change CICOYSA3 Description State State [31:0] Output format : YCbCr 4:2:2 or 4:2:0 Y 3rd frame start...
Page 613 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CB2 START ADDRESS REGISTER Register Address Description Reset Value CICOCBSA2 0x4D80_002C Cb 2 frame start address for codec DMA Initial Change CICOCBSA2 Description State State CICOCBSA2 [31:0] Cb 2 frame start address for codec DMA...
Page 614 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR CR2 START ADDRESS REGISTER Register Address Description Reset Value CICOCRSA2 0x4D80_003C Cr 2 frame start address for codec DMA Initial Change CICOCRSA2 Description State State CICOCRSA2 [31:0] Cr 2 frame start address for codec DMA...
Page 615 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CODEC TARGET FORMAT REGISTER Register Address Description Reset Value CICOTRGFMT 0x4D80_0048 Target image format of codec DMA Initial Change CICOTRGFMT Description State State [31] 1 : YCbCr 4:2:2 codec scaler input image format. 0 : YCbCr 4:2:0 codec scaler input image format. In this...
Page 616 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR X-axis flip Original image Y-axis flip 180' rotation Figure 23-16. Codec image mirror and rotation Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 617 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CODEC DMA CONTROL REGISTER Register Address Description Reset Value CICOCTRL 0x4D80_004C Codec DMA control related Initial Change CICOCTRL Description State State Reserved [31:24] [23:19] Output format : YCbCr Main burst length for codec Y frames...
Page 618 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR • Non-Interleaved burst length Main burst length = 4, 8, 16 Remained burst length = 4, 8, 16 Main burst length = 2, 4, 8, 16 Remained burst length = 2, 4, 8, 16 NOTE: When Interleave_Co = 1, there are some restricts in burst length setting as below.
Page 619 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE SourceHsize TargetHsize_xx Original Input Scale Down TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr SRC_Width = SourceHsize DST_Width = TargetHsize_xx SRC_Height = SourceVsize DST_Height = TargetVsize_xx SourceHsize TargetHsize_xx Original Input Zoom In : WinHorOfst, WinHorOfst2 TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr...
Page 620 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR If ( SRC_Height >= 64 × DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ } else if (SRC_Height >= 32 × DST_Height) { PreVerRatio_xx = 32; V_Shift = 5; } else if (SRC_Height >= 16 × DST_Height) { PreVerRatio_xx = 16; V_Shift = 4; } else if (SRC_Height >= 8 ×...
Page 621 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CODEC PRE-SCALER CONTROL REGISTER 1 Register Address Description Reset Value CICOSCPRERATI 0x4D80_0050 Codec pre-scaler ratio control Initial Change CICOSCPRERATIO Description State State SHfactor_Co [31:28] Shift factor for codec pre-scaler Reserved [27:23] PreHorRatio_Co [22:16] Horizontal ratio of codec pre-scaler...
Page 622 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR CODEC MAIN-SCALER CONTROL REGISTER Register Address Description Reset Value CICOSCCTRL 0x4D80_0058 Codec main-scaler control Initial Change CICOSCCTRL Description State State [31] Codec scaler bypass for upper 2048 x 2048 size (In this case, ImgCptEn_CoSC and ImgCptEn_PrSC should be 0, but ImgCptEn should be 1.
Page 623 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CODEC STATUS REGISTER Register Address Description Reset Value CICOSTATUS 0x4D80_0064 Codec path status Initial Change CICOSTATUS Description State State OvFiY_Co [31] Overflow state of codec FIFO Y OvFiCb_Co [30] Overflow state of codec FIFO Cb...
Page 624 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR RGB2 START ADDRESS REGISTER Register Address Description Reset Value CIPRCLRSA2 0x4D80_0070 RGB 2 frame start address for preview DMA Initial Change CIPRCLRSA2 Description State State CIPRCLRSA2 [31:0] RGB 2 frame start address for preview DMA...
Page 625 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW TARGET FORMAT REGISTER Register Address Description Reset Value CIPRTRGFMT 0x4D80_007C Target image format of preview DMA 0x8000_0000 X-axis flip Original image Y-axis flip 180' rotation Figure 23-18. Preview image mirror and rotation Initial Change...
Page 626 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR PREVIEW DMA CONTROL REGISTER Register Address Description Reset Value CIPRCTRL 0x4D80_0080 Preview DMA control related Initial Change CIPRCTRL Description State State Reserved [31:24] RGBburst1_Pr [23:19] Main burst length for preview RGB frames RGBburst2_Pr [18:14] Remained burst length for preview RGB frames...
Page 627 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW PRE-SCALER CONTROL REGISTER 1 Register Address Description Reset Value CIPRSCPRE 0x4D80_0084 Preview pre-scaler ratio control RATIO CIPRSC Description Initial Change PRERATIO State State SHfactor_Pr (v) [31:28] Shift factor for preview pre-scaler Reserved [27:23] PreHorRatio_Pr...
Page 628 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR PREVIEW MAIN-SCALER CONTROL REGISTER Register Address Description Reset Value CIPRSCCTRL 0x4D80_008C Preview main-scaler control Initial Change CIPRSCCTRL Description State State Sample_Pr (v) [31] Sampling method for format conversion. (normally 1) RGBformat_Pr [30] 1 : 24-bit RGB ,...
Page 629 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW STATUS REGISTER Register Address Description Reset Value CIPRSTATUS 0x4D80_0098 Preview path status Initial Change CIPRSTATUS Description State State OvFiCb_Pr [31] Overflow state of preview FIFO Cb OvFiCr_Pr [30] Overflow state of preview FIFO Cr...
Page 630 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR IMAGE CAPTURE ENABLE REGISTER Register Address Description Reset Value CIIMGCPT 0x4D80_00A0 Image capture enable command Initial Change CIIMGCPT Description State State ImgCptEn [31] camera interface global capture enable ImgCptEn_ [30] capture enable for codec scaler. This bit must be zero in CoSc scaler-bypass mode.
Page 631 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE CODEC CAPTURE SEQUENCE REGISTER Register Address Description Reset Value CICOCPTSEQ 0x4D80_00A4 Codec dma capture sequence related 0xFFFFFFFF CICOCPTSEQ Description Initial State [31:0] Capture sequence pattern in Codec DMA 0xFFFF_FFF Cpt_CoDMA_Seq Cpt_CoDMA_Ptr Cpt_CoDMA_Seq[31:0] ..
Page 632 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR CODEC SCAN LINE OFFSET REGISTER Register Address Description Reset Value CICOSCYOS 0x4D80_00A8 Codec scan line Y offset related Initial Change CICOSCYOS Description State State Reserved [31:29] [28:16] The number of the skipped pixels for initial offset (should be even number for word boundary alignment).
Page 633 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE SCREEN Initial offset Line offset Target image Figure 23-20. Scan line offset Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 23-41 Specifications and information herein are subject to change without notice.
Page 634 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR IMAGE EFFECTS REGISTER Register Address Description Reset Value CIIMGEFF 0x4D80_00B0 Image Effects related 0010_0080 Initial Change CIIMGEFF Description State State Reserved [31:29] [28:26] Image Effect selection 3’b000 : Bypass 3’b001 : Arbitrary Cb/Cr 3’b010 : Negative 3’b011 : Art Freeze...
Page 635 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE MSDMA Y START ADDRESS REGISTER Register Address Description Reset Value CIMSYSA 0x4D80_00B4 MSDMA Y start address related 0000_0000 Initial Change CIMSYSA Description State State Reserved [31] [30:0] DMA start address for Y component (YCbCr 4:2:0)
Page 636 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR MSDMA CB END ADDRESS REGISTER Register Address Description Reset Value CIMSCBEND 0x4D80_00C4 MSDMA Cb end address related 0000_0000 Initial Change CIMSCBEND Description State State Reserved [31] CIMSCBEND [30:0] DMA End address for Cb component (YCbCr 4:2:0)
Page 637 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE MSDMA CB OFFSET REGISTER Register Address Description Reset Value CIMSCBOFF 0x4D80_00D0 MSDMA Cb offset related 0000_0000 Initial Change CIMSCBOFF Description State State Reserved [31:24] CIMSCBOFF [23:0] Offset of Cb component for fetching source image MSDMA CR OFFSET REGISTER...
Page 638 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR - MSDMA Start address Start address of ADDRStart_Y/Cb/Cr points the first word address where the corresponding component of Y/Cb/Cr is read. Each one should be aligned with word boundary (i.e. ADDRStart_X[1:0] = 00). ADDRStart_Cb and ADDRStart_Cr are valid only for the YCbCr420 source image format.
Page 639 S3C2451X RISC MICROPROCESSOR CAMERA INTERFACE MSDMA CONTROL REGISTER Register Address Description Reset Value CIMSCTRL 0x4D80_00DC MSDMA control register 0000_0000 Initial Change CIMSCTRL Description State State Reserved [31:7] MSDMA read the saved memory data. EOF_MS When this operation done, EOF will be generated. (read...
Page 640 CAMERA INTERFACE S3C2451X RISC MICROPROCESSOR start start 0 ->1 setting 1 -> 0 setting 0 -> 1 setting ENVID_MS Figure 23-22. ENVID_MS SFR setting when DMA start to read memory data RGB start address, MSDMA Start,End,OFFSET, Preview Target format, MSDMA Source image width,...
Page 641 S3C2451X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC & TOUCH SCREEN INTERFACE OVERVIEW The 12-bit CMOS ADC (Analog to Digital Converter) is a recycling type device with 10-channel analog inputs. It converts the analog input signal into 12-bit binary digital codes at a maximum conversion rate of 1MSPS with 5MHz A/D converter clock.
Page 642 ADC AND TOUCH SCREEN INTERFACE S3C2451X RISC MICROPROCESSOR ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 24-1 shows the functional block diagram of A/D converter and touch screen interface. Note that the A/D converter device is a recycling type.
Page 643 S3C2451X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE FUNCTION DESCRIPTIONS A/D Conversion Time When the PCLK frequency is 50 MHz, the prescaler value is 49 and total 10-bit and 12-bit conversion time is given: A/D converter freq. = 50 MHz/(49+1) = 1 MHz...
Page 644 ADC AND TOUCH SCREEN INTERFACE S3C2451X RISC MICROPROCESSOR 4. Waiting for interrupt mode (ADCTSC = 0xd3) Touch screen controller generates interrupt (INT_TC) signal when the stylus is down. The value of ADC touch screen control register (ADCTSC) is ‘0xd3’; PULL_UP is ‘0’, XP_SEN is ‘1’, XM_SEN is ‘0’, YP_SEN is ‘1’ and YM_SEN is ‘1’.
Page 645 S3C2451X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL (ADCCON) REGISTER Register Address Description Reset Value ADCCON 0x58000000 ADC control register 0x3FC4 ADCCON Description Initial State ECFLG [15] End of conversion flag (read only).
Page 646 ADC AND TOUCH SCREEN INTERFACE S3C2451X RISC MICROPROCESSOR ADC TOUCH SCREEN CONTROL (ADCTSC) REGISTER Register Address Description Reset Value ADCTSC 0x58000004 ADC touch screen control register 0x058 ADCTSC Description Initial State UD_SEN Select interrupt source Stylus Up or Down 0 = Detect Stylus Down Signal.
Page 647 S3C2451X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC START DELAY (ADCDLY) REGISTER Register Address Description Reset Value ADCDLY 0x58000008 ADC start or interval delay register 0x00ff ADCDLY Description Initial State DELAY [15:0] Incase of ADC conversion mode (Normal, Separate, Auto 0x00ff conversion);...
Page 648 ADC AND TOUCH SCREEN INTERFACE S3C2451X RISC MICROPROCESSOR ADC CONVERSION DATA (ADCDAT0) REGISTER Register Address Description Reset Value ADCDAT0 0x5800000C ADC conversion data register ADCDAT0 Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode.
Page 649 S3C2451X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC CONVERSION DATA (ADCDAT1) REGISTER Register Address Description Reset Value ADCDAT1 0x58000010 ADC conversion data register ADCDAT1 Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode.
Page 650 ADC AND TOUCH SCREEN INTERFACE S3C2451X RISC MICROPROCESSOR ADC CHANNEL MUX REGISTER (ADCMUX) Register Address Description Reset Value ADCMUX 0x5800018 Analog input channel select ADCMUX Description Initial State ADCMUX [3:0] Analog input channel select. 0000 = AIN 0 0001 = AIN 1...
Page 651 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS-BUS INTERFACE OVERVIEW IIS (Inter-IC Sound) is one of the popular digital audio interface. The bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. Surely, it is possible to transmit data between two IIS bus.
Page 652 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR BLOCK DIAGRAM Figure 25-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel control block as shown in Figure 25-1. Note that each FIFO has 32-bit width and 16 depth structure, which contains left/right channel data.
Page 653 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE MASTER/SLAVE MODE Master or slave mode can be chosen by setting IMS bit of IISMOD register. In master mode, I2SSCLK and I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK by dividing.
Page 654 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR AUDIO SERIAL DATA FORMAT IIS-BUS FORMAT The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select clock I2SLRCLK, and serial bit clock I2SSCLK; the device generating I2SLRCLK and I2SSCLK is the master.
Page 655 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE Figure 25-3 shows the audio serial format of IIS, MSB-justified, and LSB-justified. Note that in this figure, the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK (BFS is 48 fs, where fs is sampling frequency;...
Page 656 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 25-1. Because RCLK is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) should be determined properly.
Page 657 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE PROGRAMMING GUIDE The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA controller. INITIALIZATION 1. Before you use IIS bus interface, you have to configure GPIOs to IIS mode. And check signal’s direction.
Page 658 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR EXAMPLE CODE TX CHANNEL The I2S TX channel provides a single stereo compliant output. The transmit channel can operate in master or Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA access.
Page 659 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 RIGHT CHANNEL LEFT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5...
Page 660 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR The Data is aligned in the TX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) LOC 0 INVALID LEFT CHANNEL LOC 1 INVALID RIGHT CHANNEL LOC 2 INVALID LEFT CHANNEL LOC 3 INVALID...
Page 661 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE RX CHANNEL The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then read this data via an APB read or a DMA access can access this data.
Page 662 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR The Data is aligned in the RX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 RIGHT CHANNEL LEFT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5...
Page 663 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) LOC 0 INVALID LEFT CHANNEL LOC 1 INVALID RIGHT CHANNEL LOC 2 INVALID LEFT CHANNEL LOC 3 INVALID...
Page 664 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE SPECIAL REGISTERS Table 25-3 Register summary of IIS interface Register Address Description Reset Value IISCON 0x55000100 IIS interface control register 0x600 IISMOD 0x55000104 IIS interface mode register IISFIC 0x55000108 IIS interface FIFO control register...
Page 665 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS CONTROL REGISTER (IISCON) Register Address Description Reset Value IISCON 0x55000100 IIS interface control register 0x0000_0600 IISCON Description [31:18] Reserved. Program to zero. FTXURSTATUS [17] TX FIFO under-run interrupt status. And this is used by interrupt clear bit.
Page 666 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR activated at any time, the channel operation will be halted after left- right channel data transfer is completed. 0: No pause operation 1: Pause operation RXCHPAUSE Rx channel operation pause command. Note that when this bit is activated at any time, the channel operation will be halted after left- right channel data transfer is completed.
Page 667 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS MODE REGISTER (IISMOD) Register Address Description Reset Value IISMOD 0x55000104 IIS interface mode register 0x0000_0000 IISMOD Description [31:15] Reserved. Program to zero. [14:13] Bit Length Control Bit Which decides transmission of 8/16 bits per...
Page 668 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR 01: 512 fs 10: 384 fs 11: 768 fs (Even in the slave mode, this bit should be set for correct) [2:1] Bit clock frequency select. 00: 32 fs, where fs is sampling frequency 01: 48 fs...
Page 669 S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE IIS FIFO CONTROL REGISTER (IISFIC) Register Address Description Reset Value IISFIC 0x55000108 IIS interface FIFO control register 0x0000_0000 IISFIC Description [31:16] Reserved. Program to zero. TFLUSH [15] TX FIFO flush command. 0: No flush, 1: Flush [14:13] Reserved.
Page 670 IIS-BUS INTERFACE S3C2451X RISC MICROPROCESSOR IIS TRANSMIT REGISTER (IISTXD) Register Address Description Reset Value IISTXD 0x55000110 IIS interface transmit data register 0x0000_0000 IISTXD Description IISTXD [31:0] TX FIFO write data. Note that the left/right channel data is allocated as the following bit fields.
Page 671 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IIS MULTI AUDIO INTERFACE OVERVIEW IIS (Inter-IC Sound) is one of the popular digital audio interface. The bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. Surely, it is possible to transmit data between two IIS bus.
Page 672 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR BLOCK DIAGRAM Figure 26-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel control block as shown in Figure 26-1. Note that each FIFO has 32-bit width and 16 depth structure, which contains left/right channel data.
Page 673 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE MASTER/SLAVE MODE Master or slave mode can be chosen by setting IMS bit of IISMOD register. In master mode, I2SSCLK and I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK by dividing.
Page 674 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR AUDIO SERIAL DATA FORMAT IIS-BUS FORMAT The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select clock I2SLRCLK, and serial bit clock I2SSCLK; the device generating I2SLRCLK and I2SSCLK is the master.
Page 675 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE Figure 26-3 shows the audio serial format of IIS, MSB-justified, and LSB-justified. Note that in this figure, the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK (BFS is 48 fs, where fs is sampling frequency;...
Page 676 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 26-1. Because RCLK is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) should be determined properly.
Page 677 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE PROGRAMMING GUIDE The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA controller. INITIALIZATION 1. Before you use IIS bus interface, you have to configure GPIOs to IIS mode. And check signal’s direction.
Page 678 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR EXAMPLE CODE TX CHANNEL The I2S TX channel provides single/double/tripple stereo compliant outputs. The transmit channel can operate in master or Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA access.
Page 679 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 RIGHT CHANNEL LEFT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4...
Page 680 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR The Data is aligned in the TX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) LOC 0 INVALID LEFT CHANNEL LOC 1 INVALID RIGHT CHANNEL LOC 2 INVALID LEFT CHANNEL LOC 3...
Page 681 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE RX CHANNEL The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then read this data via an APB read or a DMA access can access this data.
Page 682 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR The Data is aligned in the RX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 RIGHT CHANNEL LEFT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4...
Page 683 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) LOC 0 INVALID LEFT CHANNEL LOC 1 INVALID RIGHT CHANNEL LOC 2 INVALID LEFT CHANNEL LOC 3...
Page 684 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR IIS-BUS INTERFACE SPECIAL REGISTERS Table 26-3 Register summary of IIS interface Register Address Description Reset Value IISCON 0x55000000 IIS interface control register 0xC600 IISMOD 0x55000004 IIS interface mode register IISFIC 0x55000008 IIS interface FIFO control register...
Page 685 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IIS CONTROL REGISTER (IISCON) Register Address Description Reset Value IISCON 0x55000000 IIS interface control register 0x0000_C600 IISCON Description Reserved. Program to zero. Reserved [31:18] FTXURSTATUS [17] TX FIFO under-run interrupt status. And this is used by interrupt clear bit.
Page 686 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR TXDMAPAUSE Tx DMA operation pause command. Note that when this bit is activated at any time, the DMA request will be halted after current on-going DMA transfer is completed. 0: No pause DMA operation...
Page 687 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IIS MODE REGISTER (IISMOD) Register Address Description Reset Value IISMOD 0x55000004 IIS interface mode register 0x0000_0000 IISMOD Description Reserved [31:15] Reserved. Program to zero. CDD2 [21:20] Channel-2 Data Discard. Discard means zero padding. It only supports 8/16 bit mode.
Page 688 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR [9:8] Transmit or receive mode select. 00: Transmit only mode 01: Receive only mode 10: Transmit and receive simultaneous mode 11: Reserved Left/Right channel clock polarity select. 0: Low for left channel and high for right channel...
Page 689 S3C2451X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE IIS FIFO CONTROL REGISTER (IISFIC) Register Address Description Reset Value IISFIC 0x55000008 IIS interface FIFO control register 0x0000_0000 IISFIC Description [31:29] Reserved. Program to zero. FTX2CNT [28:24] TX FIFO2 data count. (0 ~ 16) [23:21] Reserved.
Page 690 IIS MULTI AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR IIS TRANSMIT REGISTER (IISTXD) Register Address Description Reset Value IISTXD 0x55000010 IIS interface transmit data register 0x0000_0000 IISTXD Description IISTXD [31:0] TX FIFO write data. Note that the left/right channel data is allocated as the following bit fields.
Page 691 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CONTROLLER OVERVIEW The AC97 Controller Unit of the S3C2451 supports the AC97 revision 2.0 features. AC97 Controller communicates with AC97 Codec using audio controller link (AC-link). Controller sends the stereo PCM data to Codec. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform.
Page 692 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER OPERATION This section explains the AC97 controller operation. Also it says to program guide. You must study AC-Link, Power-down sequence and Wake-up sequence. BLOCK DIAGRAM Figure 27-1 shows the functional block diagram of S3C2451 AC97 Controller. The AC97 signals form the AC- link, which is a point-to-point synchronous serial inter-connecting that supports full-duplex data transfers.
Page 693 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER INTERNAL DATA PATH Figure 27-2 shows the internal data path of S3C2451 AC97 Controller. It has stereo Pulse Code Modulated (PCM) In, Stereo PCM Out and mono Mic-in buffers, which consist of 16-bit, 16 entries buffer. It also has 20-bit I/O shift register via AC-link.
Page 694 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR OPERATION FLOW CHART When you initialize the AC97 controller, you must assert system reset or cold reset. Because we don’t know the previous state of the external the AC97 audio-codec. This assumes that GPIO is already ready. Then you make codec ready interrupt enable.
Page 695 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC-LINK DIGITAL INTERFACE PROTOCOL Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S3C2451 AC97 Controller. AC-link is a full-duplex, fixed-clock, PCM digital stream. It employs a time division multiplexed (TDM) scheme to handle control register accesses and multiple input and output audio streams.
Page 696 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR AC-LINK OUTPUT FRAME (SDATA_OUT) Slot 0: Tag Phase In slot 0, the first bit is a bit (SDATA_OUT, bit 15) which represents the validity of the entire frame. If bit 15 is a 1, the current frame contains at least a valid time slot. The next 12 bit positions correspond each 12 time slot contains valid data.
Page 697 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC-LINK INPUT FRAME (SDATA_IN) Slot 0: Tag Phase In slot 0, the first bit is a bit (SDATA_OUT, bit 15) that indicates whether the AC97 controller is in the CODEC ready state. If the CODEC Ready bit is a 0, the AC97 controller is not ready for normal operation. This condition is normal after the power is de-asserted on reset and the AC97 controller voltage references are settling.
Page 698 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR Slot 3: PCM Record Left channel Slot 3 which is audio input frame is the left channel audio output of the AC97 Codec. If a sample has a resolution that is less than 16 bits, the AC97 Codec fills all training non-valid bit positions in the slot with zeroes. Slot 4: PCM Right channel audio Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec.
Page 699 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC97 POWER-DOWN For details, please refer the AC-Link Power Managerment part of AC97 revision 2.0 specification. SYNC BIT_CLK slot 12 Write to Data SDATA_OUT prev.frame 0X26 slot 12 SDATA_IN prev.frame Figure 27-7. AC97 Power-down Timing Powering Down the AC-link The AC-link signals enter a low power mode when the AC97 Codec Power-down register (0x26) bit PR4 is set to a 1 (by writing 0x1000).
Page 700 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR CODEC RESET For details, please refer the CODEC Reset part of AC97 revision 2.0 specification. Cold AC97 Reset A cold reset is generated when the nRESET pin is asserted through the AC_GLBCTRL. Asserting and deasserting nRESET activates BITCLK and SDATA_OUT. All AC97 control registers are initialized to their default power on reset values.
Page 701 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CONTROLLER STATE DIAGRAM WARM IDLE ACTIVE INIT READY : PCLK rising : ACLINK_ON : CODEC_READY & TRANS_DATA & NORMAL_SYNC : ~CODEC_READY | ~TRANS_DATA : !ACLINK_ON : POWER_DOWN : WARM_RESET : CODEC_WAKEUP : COLD_RESET | ~PRESETn Figure 27-9.
Page 702 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER SPECIAL REGISTERS AC97 SPECIAL FUNCION REGISTER SUMMARY Register Address Description Reset Value AC_GLBCTRL 0x5B000000 AC97 Global Control Register 0x00000000 AC_GLBSTAT AC97 Global Status Register 0x5B000004 0x00000001 AC_CODEC_CMD AC97 Codec Command Register 0x5B000008 0x00000000 AC_CODEC_STAT 0x5B00000C AC97 Codec Status Register...
Page 703 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC97 GLOBAL CONTROL REGISTER (AC_GLBCTRL) This is the global register of the AC97 controller. There are interrupt control registers, DMA control registers, AC-Link control register, data transmission control register and related reset control register. Register Address Description Reset Value...
Page 704 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT) This is the status register. When the interrupt is occurred, you can check what the interrupt source is. Register Address Description Reset Value AC_GLBSTAT 0x5B000004 AC97 Global Status Register 0x00000001 AC_GLBSTAT Description Initial State...
Page 705 S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CODEC STATUS REGISTER (AC_CODEC_STAT) If the Read enable bit is 1 and Codec command address is valid, Codec status data is also valid. Register Address Description Reset Value AC_CODEC_STAT 0x5B00000C AC97 Codec Status Register 0x00000000 AC_CODEC_STAT Description...
Page 706 AC97 CONTROLLER S3C2451 RISC MICROPROCESSOR AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER (AC_MICADDR) To index the internal MIC-in FIFO address. Register Address Description Reset Value AC_MICADDR 0x5B000014 AC97 Mic In Channel FIFO Address Register 0x00000000 AC_MICADDR Description Initial State [31:20] Reserved.
Page 707 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM AUDIO INTERFACE OVERVIEW The S3C2451X has two ports of PCM Audio Interface. The PCM Audio Interface module provides PCM bi- directional serial interface to an external Codec. FEATURE − Mono, 16bit PCM, 2 ports audio interface.
Page 708 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input PCMSOURCE_CLK that is used to generate the serial shift timing. The PCM interface outputs a serial data out, a serial shift clock, and a sync signal.
Page 709 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM TIMING The following figures show the timing relationship for the PCM transfers. Figure 28-1 shows a PCM transfer with the MSB configured to be coincident with the PCMFSYNC. This MSB positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 0.
Page 710 CTL_SERCLK_SEL Figure 28-3 Input Clock Diagram for PCM S3C2451X PCM is able to select clock either PCLK or External Clock. Refer figure 28-3. To enable clock gating, please refer to the SYSCON part(SCLKCON, PCLKCON). Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 711 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM REGISTERS There are 8 control registers for each PCM port. (Since there are two ports, the total number of control registers is 16.) The number(0 or 1) that follows each register name indicates which PCM module this register belongs to.
Page 712 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR PCM CONTROL REGISTER The PCM_CTL register is used to control the various aspects of the PCM module. It also provides a status bit to provide the option to using polling instead of interrupt based control.
Page 713 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE Initial PCM_CTLn Description State RXFIFO_DIPSTICK [12:7] Determines when the almost_full, almost_empty flags go active for the RXFIFO RXFIFO_ALMOST_EMPTY : fifo_depth < fifo_dipstick RXFIFO_ALMOST_FULL : fifo_depth > (32 – fifo_dipstick) NOTE: - If fifo_dipstick is 0, Almost_empty, Almost_full are invalid.
Page 714 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR Initial PCM_CTLn Description State PCM enable signal. PCM_PCM_ENABLE 1: Enables the serial shift state machines. The enable must be set HIGH for the PCM to operate. 0: The PCMSOUT will not toggle. The internal divider-counters(serial shift register’s counter) are held in reset.
Page 715 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM CLK CONTROL REGISTER Register Address Description Reset Value PCM_CLKCTL0 0x5C000004 Control the PCM0 Audio Inteface 0x00000000 PCM_CLKCTL1 0x5C000104 Control the PCM1 Audio Inteface 0x00000000 The bit definitions for the PCM_CTL Control Register are shown below:...
Page 716 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR The PCM Tx FIFO REGISTER Register Address Description Reset Value PCM0 interface Transmit FIFO data PCM_TXFIFO0 0x5C000008 0x00010000 register PCM1 interface Transmit FIFO data PCM_TXFIFO1 0x5C000108 0x00010000 register The bit definitions for the PCM_TXFIFO Register are shown below:...
Page 717 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM R FIFO REGISTER Register Address Description Reset Value PCM0 interface Receive FIFO data PCM_RXFIFO0 0x5C00000C 0x00010000 register PCM1 interface Receive FIFO data PCM_RXFIFO1 0x5C00010C 0x00010000 register The bit definitions for the PCM_RXFIFO Register are shown below:...
Page 718 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR PCM INTERRUPT CONTROL REGISTER The PCM_IRQ_CTL register is used to control the various aspects of the PCM interrupts. Register Address Description Reset Value PCM_IRQ_CTL0 0x5C000010 Control the PCM0 Interrupts 0x00000000 PCM_IRQ_CTL1 0x5C000110 Control the PCM1 Interrupts...
Page 719 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM_IRQ_CTLn Description Initial State TXFIFO_ERROR_ Interrupt is generated for TxFIFO starve ERROR. STARVE This occurs whenever the TxFIFO is read when it is still empty. This is considered an ERROR and will have unexpected results...
Page 720 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR PCM_IRQ_CTLn Description Initial State RXFIFO_ERROR_ Interrupt is generated for RxFIFO overflow ERROR. OVERFLOW This occurs whenever the RxFIFO is written when it is already full. This is considered an ERROR and will have unexpected...
Page 721 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM INTERRUPT STATUS REGISTER The PCM_IRQ_STAT register is used to report IRQ status. Register Address Description Reset Value PCM_IRQ_STAT0 0x5C000014 PCM0 Interrupt Status 0x00000000 PCM_IRQ_STAT1 0x5C000114 PCM1 Interrupt Status 0x00000000 The bit definitions for the PCM_IRQ_STATUS Register are described below:...
Page 722 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR PCM_IRQ_STATn Description Initial State TXFIFO_ERROR Interrupt is generated for TX FIFO overflow ERROR. _OVERFLOW This occurs whenever the TX FIFO is written when it is already full. This is considered as an ERROR and will have unexpected results 1: IRQ is occurred.
Page 723 S3C2451X RISC MICROPROCESSOR PCM AUDIO INTERFACE PCM FIFO STATUS REGISTER The PCM_FIFO_STAT register is used to report FIFO status. Register Address Description Reset Value PCM_FIFO_STAT0 0x5C000018 PCM0 FIFO Status 0x00000000 PCM_FIFO_STAT1 0x5C000118 PCM1 FIFO Status 0x00000000 The bit definitions for the PCM_FIFO_STATUS Register are shown below:...
Page 724 PCM AUDIO INTERFACE S3C2451X RISC MICROPROCESSOR PCM INTERRUPT CLEAR REGISTER The PCM_CLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing interrupt asserted. Writing any values on this register clears interrupts for ARM. Reading this register is not allowed.
Page 725 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 29-1. Absolute Maximum Rating Parameter Symbol Unit VDDi, VDDiarm, VDDalive, VDDA_MPLL, VDDA_EPLL, -0.5 VDDI_UDEV DC Supply Voltage VDD_OP1,VDD_OP2,VDD_RTC, VDD_SDRAM,VDD_SRAM, -0.5 VDD_CAM,VDD_SD,VDDA_ADC,V DDA33x DC Input Voltage -0.5 DC Output Voltage VOUT -0.5...
Page 726 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR RECOMMENDED OPERATING CONDITIONS Table 29-2. Recommended Operating Conditions (400MHz) Parameter Symbol Unit DC Supply Voltage for Alive Block VDDalive 1.15 1.25 DC Supply Voltage for Core Block ARMCLK / HCLK VDDiarm 400/133 VDDi VDDA_MPLL (TBD)
Page 727 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-2. Recommended Operating Conditions (533MHz) Parameter Symbol Unit DC Supply Voltage for Alive Block VDDalive 1.15 1.25 DC Supply Voltage for Core Block ARMCLK / HCLK VDDiarm 533/133 VDDi VDDA_MPLL VDDA_EPLL VDDiarm 133/133 VDDi...
Page 728 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR D.C. ELECTRICAL CHARACTERISTICS Table 29-3. Normal I/O PAD DC Electrical Characteristics Symbol Parameter Unit 3.3V VDD_OP Output Supply Voltage 2.5V 1.8V 1.65 1.95 400MHz 1.3(TBD) VDDi Internal Core Voltage 533MHz °C Temp Ambient Temperature dc Input Logic High 0.7*VDD_OP...
Page 729 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-4. Special Memory DDR I/O PAD DC Electrical Characteristics Symbol Parameter Unit Note VDD_ Output supply voltage 1.70 1.90 sdram 400MHz 1.3(TBD) VDDi Internal Core Voltage 533MHz °C Temp Ambient Temperature 0.8*VDD dc Input Logic High sdram 0.2*VDD...
Page 730 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR A.C. ELECTRICAL CHARACTERISTICS XTALCYC 1/2 VDD_OP1 1/2 VDD_OP1 NOTE: The clock input from the X pin. TIpll Figure 29-1. XTIpll Clock Timing EXTCYC EXTHIGH EXTLOW 1/2 VDD_OP1 1/2 VDD_OP1 NOTE: The clock input from the EXTCLK pin.
Page 731 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA HCLK (internal) HC2CK CLKOUT (HCLK) HC2SCLK SCLK Figure 29-4. HCLK/CLKOUT/SCLK in case that EXTCLK is used EXTCLK RESW nRESET Figure 29-5. Manual Reset Input Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 732 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Power PLL can operate after OM[3:2] is latched. nRESET XTIpll or EXTCLK PLL is configured by S/W first time. tPLL Clock Disable VCO is adapted to new clock frequency. output tRST2RUN FCLK MCU operates by XTIpll FCLK is new frequency.
Page 733 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK XTIpll Wake up from sleep mode Clock Disable tOSC2 Output Several slow clocks (XTIpll or EXTCLK) FCLK Sleep mode is initiated. Figure 29-7. Sleep Mode Return Oscillation Setting Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 734 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Figure 29-8. SMC Synchronous Read Timing Figure 29-9. SMC Asynchronous Read Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 29-10 Specifications and information herein are subject to change without notice.
Page 735 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Asynchronous Write SMCLK tADDRD_A RADDR tDOD_A RDATA D(A) tCSD_A nRCS tWED nRWE Figure 29-10. SMC Asynchronous Write Timing Figure 29-11. SMC Synchronous Write Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 736 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR S M C LK R A D D R [26 :0] R D A T A D (A ) [31 :0] nR C S nR O E nW A IT tH S tW S Figure 29-12. SMC Wait Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 737 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA TACLS TWRPH0 TWRPH1 HCLK tCLED tCLED FCLE tWED tWED nFWE tWDD tWDD RDATA COMMAND [15:0] TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK HCLK tALED tALED tALED tALED FALE FALE tWED tWED tWED tWED nFWE nFWE...
Page 738 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Figure 29-14. SDRAM READ / WRITE Timing (Trp = 2, Trcd = 2, Tcl = 2, DW = 16-bit) Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 739 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE tSAD tSAD SADDR tSAD A10/AP tSCSD tSCSD nSCSx tSRD tSRD nSRAS tSCD nSCAS DQMx tSWD tSWD nSWE SDATA 'HZ' Figure 29-15. SDRAM MRS Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 740 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR SCLK SCKE tSAD tSAD SADDR tSAD A10/AP tSCSD tSCSD nSCSx tSRD tSRD nSRAS tSCD nSCAS DQMx tSWD nSWE SDATA 'HZ' NOTE: Before executing auto/self refresh command, all banks must be in idle state. Figure 29-16. SDRAM Auto Refresh Timing (Trp = 2, Trc = 4) Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 741 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA HCLK tXRS nXDREQ tXRS tXAD tCADH nXDACK Read Write Min. 3SCLK tCADL Figure 29-17. External DMA Timing (Handshake, Single transfer) Tf2hsetup VSYNC Tf2hhold HSYNC Tvfpd Tvspw Tvbpd VDEN HSYNC Tl2csetup Tvclkh Tvclk VCLK Tvclkl Tvdhold...
Page 742 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR I2SLRCLK(Output) LRId I2SSCLK(Output) I2SSDO(Output) Figure 29-19. IIS Interface Timing (I2S Master Mode Only) I2SLRCLK(Input) LRId I2SSCLK(Input) I2SSDI(Input) Figure 29-20. IIS Interface Timing (I2S Slave Mode Only) fSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSDAS tSDAH tSTARTS IICSDA Figure 29-21.
Page 743 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Figure 29-22. SD/MMC Interface Timing SD0_CLK tHSDCD SD0_CMD(out) tHSDCS tHSDCH SD0_CMD(in) tHSDDD SD0_DAT[7:0](out) tHSDDS tHSDDH SD0_DAT[7:0](in) Figure 29-23. High Speed SDMMC Interface Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 744 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR SPICLK tSPIMOD SPIMOSI (MO) tSPISIS tSPISIH SPIMOSI (SI) tSPISOD SPIMISO (SO) tSPIMIS tSPIMIH SPIMISO (MI) Figure 29-24. SPI Interface Timing (CPHA = 1, CPOL = 1) SPICLK SPIMOSI (MO) tSPIMIH tSPIMOD SPIMISO (MI) tSPIMIS SPIMISO (SO)
Page 745 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Rise Time Fall Time VCRS Differential Data Lines Figure 29-26. USB Timing (Data signal rise/fall time) Figure 29-27. PCM Interface Timing Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available.
Page 746 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Table 29-12. Clock Timing Constants (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP1 = 3.3V ± 0.3V) Parameter Symbol Unit Crystal clock input frequency XTAL Crystal clock input cycle time...
Page 747 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-13. SMC Timing Constants (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_SRAM = 1.8V ± 0.1V) Parameter Symbol Unit SMC Chip Select Delay tCSD bank0 – bank1...
Page 748 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Table 29-15. Memory Interface Timing Constants (SDRAM) (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_SDRAM = 1.8V ± 0.1V, 133MHz, CL = 25pF) Parameter Symbol Unit SDRAM Address Delay 1.58...
Page 749 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-16. DMA Controller Module Signal Timing Constants (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP2 = 3.3V ± 0.3V) Parameter Symbol Unit eXternal Request Setup 6.4/6.4 –...
Page 750 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Table 29-19. IIS Controller Module Signal Timing Constants(I2S Slave Mode Only) (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = –40 to 85 °C, VDD_OP2 = 3.3V ± 0.3V) Parameter Symbol Min. Typ.
Page 751 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-21. SD/MMC Interface Transmit/Receive Timing Constants (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_SD = 3.3V ± 0.3V) Parameter Symbol Typ. Unit SD Command output Delay time –...
Page 752 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Table 29-24. USB Electrical Specifications (VDD12V = 1.2V ± 5%, TA = -40 to 85°C, VDDA33x = 3.3V ± 0.3V) Parameter Symbol Condition Unit Supply Current Suspend Device ICCS µA Leakage Current Hi-Z state Input Leakage 0V <...
Page 753 S3C2451X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-25. USB Full Speed Output Buffer Electrical Characteristics (VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDDA33x = 3.3V ± 0.3V) Parameter Symbol Condition Unit Driver Characteristics Transition Time...
Page 754 ELECTRICAL DATA S3C2451X RISC MICROPROCESSOR Table 29-28. PCM Interface Timing (VDDI= 1.0V± 0.05V, TA = -40 to 85°C, VDD = 3.3V ± 0.3V, 2.5V ± 0.2V, 1.8V ± 0.1V) Parameter Symbol Min. Typ. Unit PCMSCLK clock width 0.128 8.192 PCMSCLK to PCMFSYNC delay...
Page 755 S3C2451X RISC MICROPROCESSOR MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSIONS Figure 30-1. 380-FBGA-1414 Package Dimension 1 (Top View) Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 30-1 Specifications and information herein are subject to change without notice.
Page 756 MECHANICAL DATA S3C2451X RISC MICROPROCESSOR Figure 30-2. 380-FBGA-1414 Package Dimension 2 (Bottom View) Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. 30-2 Specifications and information herein are subject to change without notice.

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