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S3C6400
RISC MICROPROCESSOR
PCLK
INT4tmp
DMAreq_en
DMAACK
DMAREQ
The table below shows the action of each Timer at the completion of the down-count as a function of the DMA
mode configuration:
DMA mode
DMA request
0 0 0
No Select
0 0 1
Timer 0
0 1 0
Timer 1
0 1 1
Timer 2
1 0 0
Timer 3
1 0 1
Timer 4
1 1 0
No Select
1 0 1
Figure 32-11: DMA Operation
INT0
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
Table 32-2: DMA Request Assertion and Interrupt Status
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INT1
INT2
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
Pulse Width Modulation Timer
INT3
INT4
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
ON if enabled
32-13
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