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S3C6400X RISC MICROPROCESSOR
nWAIT PIN OPERATION
If the WAIT operation corresponding to each memory bank is enabled, the nOE duration will be prolonged by the
external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at
the next clock after sampling nWAIT is high. The nWE signal have the same relation with nOE.
HCLK
ADDR
nGCS
nOE
nWAIT
DATA(R)
Tacs
Tcos
Figure 6-2 SROM Controller nWAIT Timing Block Diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
tRC
Tacc=4
SROM CONTROLLER
Delayed
Sampling nWAIT
6-3
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