Samsung S3C6400X User Manual page 995

IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS LINE CONTROL (IICLC) REGISTER
Register
IICLC 0x7F004010
IICLC
Filter enable
SDA output delay
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
30-14
Specifications and information herein are subject to change without notice.
Address R/W
R/W
Bit
[2] IIC-bus filter enable bit.
When SDA port is operating as input, this bit should be High.
This filter can prevent from occurred error by a glitch during
double of PCLK time.
0: Filter disable
1: Filter enable
[1:0] IIC-Bus SDA line delay length selection bits.
SDA line is delayed as following clock time(PCLK)
00: 0 clocks
10: 10 clocks
Description
IIC-Bus multi-master line control register
Description
01: 5 clocks
11: 15 clocks
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
0x00
0
00