Samsung S3C6400X User Manual page 961

S3C6400X RISC MICROPROCESSOR
Bits Name
[31:1] Reserved
[0] Sw_rst
CHID_REG
CHID_REG is used to transfer channel ID.
Address = BASEADDR + 0x18 (0x7E00_6018)
Bits Name
[31] Break_frame
[30] Auto_clr
[29] Br_frame_clr
[28:3] Reserved
[2:0] CHID
Note: In order to send data with a constant channel ID, the CHID_REG must be set only once and then the data
to be transfered are pushed into the data fifo. Then the same channel ID is attached to each of the data with sent
through TxDATA. If the channel ID is different from the previous transfer, you must set the new channel ID into the
CHID_REG before pushing data into the data fifo. Break frame is sent to Rx side when '1' is inputted for the
Break_frame bit in the frame mode. This bit is automatically cleared after the transmission is completed (36 '0's
are transffered) in the auto clear mode (auto clear bit =0). In this case, the internal state goes to IDLE state. If not
in the auto clear mode, the TxDATA continues to transfer '0' while the internal state maintained in TxBRK state.
Meanwhile, if the br_frame_clr bit is written as '1', the state changes from RxBRK to IDLE and the TxDATA stops
to transfer '0's.
DATA_REG
DATA_REG is TxFIFO input.
Reserved bits
Software reset
0 : set
Table 28-10 SWRST_REG register description
Description
Break frame transfer in Frame mode
In auto clear mode, this bit is automatically
cleared.
But the other mode, TxDATA send '0' stream
during setting '1' at br_frame_clr bit .
Break frame auto clear bit
0 : auto clear & TxBRK state end
1 : auto clear disable & TxBRK state continue
Stop break frame continuing transfer
Reserved bits
Channel ID
Table 28-11 CHID_REG register description
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
1 : reset
MIPI HSI
R/W Reset Value
R 0x00000000
R/W 0x0
R/W Reset Value
R/W/C 0x0
R/W 0x0
W 0x0
R 0x0000000
R/W 0x0
28-17