Samsung S3C6400X User Manual page 836

S3C6400X RISC MICROPROCESSOR
Sof
OTGInt
ModeMis
CurMod
CORE INTERRUPT MASK REGISTER (GINTMSK)
This register works with the Core Interrupt register to interrupt the application. When an interrupt bit is masked,
the interrupt associated with that bit will not be generated. However, the Core Interrupt (GINTSTS) register bit
corresponding to that interrupt will still be set.
· Mask interrupt : 1'b0
· Unmask interrupt :1'b1
Register Address
GINTMSK 0x7C00_0018
GINTMSK
WkUpIntMsk
SessReqIntMsk
DisconnIntMsk
[3] R_SS_ Start of (micro) Frame
WC In Host mode, the core sets this bit to indicate that
an SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is
transmitted on the USB. The application must write a
1 to this bit to clear the interrupt. In Device mode, in
the core sets this bit to indicate that an SOF token
has been received on the USB. The application can
read the Device Status register to get the current
(micro)frame number. This interrupt is seen only
when the core is operating at either HS or FS.
[2] RO OTG Interrupt
The core sets this bit to indicate an OTG protocol
event. The application must read the OTG Interrupt
Status (GOTGINT) register to determine the exact
event that caused this interrupt. The application must
clear the appropriate status bit in the GOTGINT
register to clear this bit.
[1] R_SS_ Mode Mismatch Interrupt
WC The core sets this bit when the application is trying to
access:
· A Host mode register, when the core is operating in
Device mode
· A Device mode register, when the core is operating
in Host mode
[0] RO Current Mode Of Operation
Indicates the current mode of operation.
· 1'b0 : Device mode
· 1'b1 : Host mode
R/W
R/W
Bit R/W
[31] R_W Resume/Remote Wakeup Detected Interrupt Mask
[30] R_W Session Request/New Session Detected Interrupt
Mask
[29] R_W Disconnect Detected Interrupt Mask
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Core Interrupt Mask Register
Description
USB2.0 HS OTG
1'b0
1'b0
1'b0
1'b0
Reset Value
32 bits
Initial State
1'b0
1'b0
1'b0
26-29