Samsung S3C6400X User Manual page 795

HOST INTERFACE
Control1 Register (CTRL1)
BSEL[3:0] = 0001, MP_A[1:0] = 00, R/W, Reset value = 0x0000
Field
Reserved
Reserved
DAMT
Interrupt Enable1 Register (INTE1)
BSEL[3:0] = 0001, MP_A[1:0] = 01, R/W, Reset value = 0x0000
Field
Reserved
IMB_EMPTY
OMB_FILLED
Status1 Register (STAT1)
BSEL[3:0] = 0001, MP_A[1:0] = 10, R/W, Reset value = 0x0002
Field
Reserved
IMB_EMPTY
OMB_FILLED
24-18
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit
[15:4]
[3:2]
[1:0] CPUIF Hold Margin Delay Amount
In order to gurantee the hold timing, address and data signals
are delayed.
00 = 5ns delay (Default)
01 = 3ns delay
10 = 1ns delay
11 = 0ns delay
Bit
[15:2]
[1] IMB empty interrupt enable
Interrupt occurs when INTE1 [1] = 1 and STAT1 [1] = 1.
[0] OMB filled interrupt enable
Interrupt occurs when INTE1 [0] = 1 and STAT1 [0] = 1.
Bit
[15:2]
[1] IMB (In-Mail Box) empty flag
This flag is an inversion of the IMB_FILLED (ie,
CPUIFC_STAT2[17]).
[0] OMB (Out-Mail Box) filled flag
This flag is set when the out-mailbox is written by SFR
access. In order to clear this flag, HIGH value must be
written in this bit.
S3C6400X
Description
Description
Description
RISC MICROPROCESSOR
Initial State
0x000
00
00
Initial State
0
0
0
Initial
State
0
1
0