Samsung S3C6400X User Manual page 544

GRAPHICS 2D
INDIVIDUAL REGISTER DESCRIPTION
GENERAL INTERRUPT ENABLE REGISTER (INTEN_REG)
Register
INTEN_REG 0x76100004
INTEN_REG Bit
Reserved [31:10]
DF [10]
F [9]
OV [8]
Reserved [7:1]
E [0]
GENERAL FIFO INTERRUPT CONTROL REGISTER (FIFO_INTC_REG)
Register
FIFO_INTC_REG 0x76100008
FIFO_INTC_REG Bit
Reserved [31:6]
FIFO_INT_LEVEL [5:0]
GENERAL INTERRUPT CONTROL PENDING REGISTER (INT_PEND_REG)
Register
INTC_PEND_REG 0x7610000C
18-12
Offset R/W
R/W Interrupt Enable register.
Drawing Engine Finished Interrupt Enable.
All command Finished Interrupt Enable. When all commands are
executed (no command in the Command FIFO), this bit will be set.
Overflow Interrupt Enable. When the Command FIFO overflows, this
bit will be set.
FIFO level Interrupt Enable. ; If E bit is set to 1, when
FIFO_INT_LEVEL is same with FIFO_NO_USED, Graphics Engine
makes INTREQ signal high.
Offset R/W
R/W Interrupt Control register
Graphics Engine requests interrupt when the number of FIFO used
is FIFO_INT_LEVEL and Interrupt Enable bit is set to 1.
Offset R/W
R/W Interrupt Control Pending register.
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Description
Description
Reset Value
0x0000_0000
Initial State
0x0
0x0
0x0
0x0
0x0
Reset Value
0x0000_0018
Initial State
0x0
0x18
Reset Value
0x0000_0000