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ONENAND CONTROLLER
INTERRUPT MONITOR CYCLE REGISTER
Register
INT_MON_CYC0
INT_MON_CYC1
INT_MON_CYCn
Reserved
INT_MON_CYC
ACCESS CLOCK REGISTER
Register
ACC_CLOCK0
ACC_CLOCK1
ACC_CLOCKn
Reserved
ACCESS_CLK
SLOW READ PATH REGISTER
Register
SLOW_RD_PATH0
SLOW_RD_PATH1
SLOW_RD_PATHn
Reserved
SRP
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-30
Specifications and information herein are subject to change without notice.
Address
R/W
0x701001B0
R/W Bank0 Interrupt Monitor Cycle Count Register
0x701801B0
Bit
[31:12]
[11:0]
Sets the number of cycles in between checks of the
INT_ERR_STAT register and the memory device's status
register. This register is only used if the Flash configuration
register bit IOBE is clear.
Address
R/W
0x701001C0
R/W Bank0 Access Clock Register
0x701801C0
Bit
[31:3]
[2:0]
Sets the number of cycles required to cover the access time of
the Flash memory device. Follows the formula
(35ns/(Xm0SMCLK Period)+1).
Flash Core
Clock (MHz)
133
100
60
Address
R/W
0x701001D0
R/W Bank0 Slow Read Path Register
0x701801D0
Bit
[31:1]
[0]
Delays the read data capture by 1/2 cycle to accommodate
the board delay. Default is 0x0.
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Description
Interface Clock (MHz)
66.5
50
30
Description
Description
Reset Value
0x01F4
Initial State
0
500
Reset Value
0x0003
Initial State
0
3
ACCESS_CL
K
3
2
2
Reset Value
0x0000
Initial State
0
0
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