Samsung S3C6400X User Manual page 760

S3C6400X RISC MICROPROCESSOR
HDCTBLG1
Reserved
H_AC_G_val1
Note: Address offset is increased as 0x04(word addressing).
IMGADDR0
Register
IMGADDR0
IMGADDR0
Image_addr0
IMGADDR1
Register
IMGADDR1
IMGADDR1
Image_addr1
IMGADDR0 and IMGADDR1 are the start address of an image data. The data before compression are read from
this address on encode mode, and decompressed data are stored from this address. It is needed when MISC[7:5]
is 0x1 or 0x2.
If process (encoding or decoding) is ended, IMG_ADDR0 or IMG_ADDR1 are swapped.
HUFADDR0
Register
HUFADDR0
Bit R/W
Reserved
[31:8] -
It defines the group number of the order for occurrence in AC
[7:0] W
Huffman table 1. The user must write some value in this.
Address
0x78801000 Source or destination image address 0
Bit R/W
[31:0] R/W Source or destination Image address 0
Address
0x78801004 Source or destination image address 1
Bit R/W
[31:0] R/W Source or destination Image address 1
Address
0x78801008 Source or destination JPEG file address 0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
Description
Description
JPEG CODEC
Reset Value
0x0000_0000
Reset Value
0x0000_0000
Reset Value
0x0000_0000
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