Samsung S3C6400X User Manual page 890

HSMMC CONTROLLER
Not Using DMA
(1)
(2)
Set Block Count Reg
(3)
(4)
Set Transfer Mode Reg
(10-W)
(11-W)
Clr Buffer Write Ready Status
(12-W)
(13-W)
Single or Multi
block transfer
(15)
Wait for Transfer Complete Int
(16)
Clr Transfer Complete Status
Figure 27-11. Transaction Control with Data Transfer Using DAT Line Sequence (Not using DMA)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-14
Specifications and information herein are subject to change without notice.
START
Set Block Size Reg
Set Argument Reg
(9)
write
Write or Read ?
Wait for Buffer Write
Ready Int
Buffer Write Ready
Int occur
Set Block Data
yes
More Blocks ?
no
(14)
Single / Multi /Infinite Block
Transfer ?
END
(5)
Set Command Reg
(6)
Wait for Command
Complete Int
Command Complete Int occur
(7)
Clr Command Complete
Status
(8)
Get Response Data
read
(10-R)
Wait for Buffer Read
Ready Int
Buffer Read Ready
(11-R)
Int occur
Clr Buffer Read Ready Status
(12-R)
Get Block Data
(13-R)
yes
More Blocks ?
no
Infinite block
transfer
(17)
Abort Transaction
S3C6400X RISC MICROPROCESSOR