Samsung S3C6400X User Manual page 992

S3C6400X RISC MICROPROCESSOR
IIC-BUS INTERFACE SPECIAL REGISTERS
MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER
Register
IICCON 0x7F004000
IICCON
Acknowledge generation
Tx clock source selection
(5)
Tx/Rx Interrupt
(2) (3)
Interrupt pending flag
(4)
Transmit clock value
Note:
1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the
STOP condition in Rx mode.
2. An IIC-bus interrupt occurs 1) when a 1-byte transmits or a receive operation is completed, 2) when a general call or a
slave
address match occurs, or 3) if bus arbitration fails.
3. To adjust the setup time of SDA before SCL rising edge, IICDS has to be written before clearing the IIC interrupt
pending bit.
4. IICCLK is determined by IICCON [6].
Tx clock can vary by SCL transition time.
When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available.
5. If the IICCON[5]=0, IICCON[4] does not operate correctly.
So, It is recommended that you set IICCON[5]=1, although you does not use the IIC interrupt.
Address R/W
R/W
Bit
(1)
[7] IIC-bus acknowledge enable bit.
0: Disable
1: Enable
In Tx mode, the IICSDA is free in the ack time.
In Rx mode, the IICSDA is L in the ack time.
[6] Source clock of IIC-bus transmit clock prescaler
selection bit.
0: IICCLK = fPCLK /16
1: IICCLK = fPCLK /512
[5] IIC-Bus Tx/Rx interrupt enable/disable bit.
0: Disable,
[4] IIC-bus Tx/Rx interrupt pending flag. This bit cannot be
written to 1. When this bit is read as 1, the IICSCL is
tied to L and the IIC is stopped. To resume the
operation, clear this bit as 0.
0: 1) No interrupt pending (when read).
2) Clear pending condition &
1: 1) Interrupt is pending (when read)
2) N/A (when write)
[3:0] IIC-Bus transmit clock prescaler.
IIC-Bus transmit clock frequency is determined by this
4-bit prescaler value, according to the following
formula:
Tx clock = IICCLK/(IICCON[3:0]+1).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIC-Bus control register
Description
1: Enable
Resume the operation (when write).
IIC-BUS INTERFACE
Reset Value
0x0X
Initial State
0
0
0
0
Undefined
30-11