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S3C6400X RISC MICROPROCESSOR
ATA_SWRST
Register
ATA_SWRST
0x7030190C
ATA_SWRST
Reserved
ATA_SWRSTN
ATA_IRQ
Register
ATA_IRQ
0x70301910
ATA_IRQ
Reserved
SBUF_EMPTY_INT
TBUF_FULL_INT
ATADEV_IRQ_INT
UDMA_HOLD_INT
XFR_DONE_INT
Note: All interrupts from ATA interface are level-triggered. Therefore, IRQ clear operation is necessary when
driver is implemented.
Note: In DMA mode, XFR_DONE_INT must be used to check the DMA transfer done. When
XFR_DONE_INT occurs, ATA_STATUS[1:0] must be idle state(2'b00). Otherwise, delay will be required until
ATA_STATUS[1:0] is set to idle state(2'b00) by hardware.
Address
Bits
[31:1]
Reserved bits
[0]
Software reset for the ATAPI host
0: No reset
1: Software reset for all ATAPI host module.
After software reset, to continue transfer, you must
configure all registers of host controller and device
registers.
Address
Bits
[31:5]
Reserved bits
[4]
When source buffer is empty.
CPU can clear this interrupt by writing "1".
[3]
When track buffer is half full.
CPU can clear this interrupt by writing "1".
[2]
When ATAPI device generates interrupt.
CPU can clear this interrupt by writing "1".
[1]
When ATAPI device makes early termination in
UDMA class. CPU can clear this interrupt by
writing "1".
[0]
When all data transfers are finished.
CPU can clear this interrupt by writing "1".
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
ATA software reset
Description
Description
ATA interrupt source
Description
CF CONTROLLER
Reset Value
0x0000_0000
R/W
Reset
Value
R
0x0
R/W
0x0
Reset Value
0x0000_0000
R/W
Reset
Value
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
9-23
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