Samsung S3C6400X User Manual page 307

S3C6400 RISC MICROPROCESSOR
Disabling a DMA channel
A DMA channel can be disabled in following three ways:
Write directly to the Channel Enable bit. Any outstanding data in the FIFOs will be lost if this method is
used.
Use the Active and Halt bits in conjunction with the Channel Enable bit.
Wait until the transfer completes. The channel is disabled automatically.
Disabling a DMA channel and losing data in the FIFO:
Clear the relevant Channel Enable bit in the relevant channel configuration register. The current AHB transfers (if
one is in progress) complete and the channel is disabled. Any data in the FIFO is lost.
Disabling a DMA channel without losing data in the FIFO:
Steps to disable a DMA channel without losing data in the FIFO:
1. Set the Halt bit in the relevant channel configuration register. This ignores any further DMA requests.
2. Poll the Active bit in the relevant channel configuration register until it reaches. This bit indicates whether there is
any data in the channel which has to be transferred.
3. Clear the Channel Enable bit in the relevant channel configuration register.
Set up a new DMA transfer
Steps to set up a new DMA transfer:
1. If the channel is not set aside for the DMA transaction:
a. Read the DMACEnbldChns controller register and find out which channels are inactive.
b. Select an inactive channel which has the required priority.
2. Program the DMA controller.
Halting a DMA channel
Set the Halt bit in the relevant DMA channel configuration register. The current source request is serviced. Any
further source DMA requests are ignored until the Halt bit is cleared.
Programming a DMA channel
Steps to program a DMA channel:
1. Decide whether use secure DMAC(SDMAC) or general DMAC(DMAC). In order to use general DMAC, disable
secure DMA control register(SDMA_SEL) of system controller. (Reset value is SDMAC)
2. Select a free DMA channel with the priority needed. Where DMA channel 0 has the highest priority and DMA
channel 7 the lowest priority.
3. Clear any pending interrupts on the channel to be used by writing to the DMACIntTCClr and DMACIntErrClr
registers. The previous channel operation might have left interrupts active.
4. Write the source address into the DMACCxSrcAddr register.
5. Write the destination address into the DMACCxDestAddr register.
6. Write the address of the next LLI into the DMACCxLLI register. If the transfer comprises of a single packet of data
then must be written into this register.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DMA
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