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S3C6400X RISC MICROPROCESSOR
Clock generation for IrDA, USB host
Figure 3-13 shows the clock generator for IrDA and USB host. Usually USB interface requires 48MHz operating
clock and the direct 48MHz path from USB-OTG is inserted for this purpose as shown in Figure 3-13.
Clock ON/OFF control
As shown in the above figures, HCLK_GATE, PCLK_GATE, and SCLK_GATE control the clock operation. If a bit
is set, the corresponding clock will be supplied through each clock divider. Otherwise, it will be masked.
HCLK_GATE controls HCLK for each IPs. The AHB interface logic of each IP is masked independently to reduce
dynamic power consumption. PCLK_GATE controls PCLK for each IP's. Few IP's require special clocks to
operate correctly. The clocks are controlled by SCLK_GATE.
Clock output
S3C6400X has clock output port, which generate internal clock. This clock is used for regular interrupt or
debugging purpose. For more information, please refer to CLK_OUT register section.
LOW POWER MODE OPERATION
S3C6400X supports low power application through low power mode operation as shown in Table 3-3. There are
four power states, which are normal state, retention state, power gating state, and power off state. All internal
logics including F/Fs and memory are running at normal state. Retention state reduces unwanted power
consumption during STOP/DEEP-STOP mode, however, retains previous states and supports fast wake-up time
from STOP/DEEP-STOP mode. Some blocks, which are DOMAIN-V, DOMAIN-I, DOMAIN-P, DOMAIN-F, and
DOMAIN-S, have no state retention feature. They can be power gating to reduce power consumption through an
internal power switch circuitry. The response time of the internal circuitry, about several usec, is faster than that of
an external power regulator. In SLEEP mode, an external regulator will be OFF to reduce power consumption and
S3C6400X minimizes power consumption and lost all information except ALIVE and RTC block. Table 3-3
summarizes four power states for S3C6400X.
State
Normal
ON
Retention
ON
Power gating
ON
Power off
OFF
Figure 3-13. IrDA/USB host clock generation
Table 3-3. Four power states for S3C6400X
External regulator
Normal operation
Retain previous state
Lost previous state
Lost previous state
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Internal F/F
Normal operation
Retain previous state
Lost previous state
Lost previous state
SYSTEM CONTROLLER
Internal Memory
3-11
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