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ONENAND CONTROLLER
TSRF
DBS-DFS WIDTH REGISTER
Register
DBS_DFS_WIDTH0
DBS_DFS_WIDTH1
DBS_DFS_WIDTHn
Reserved
WIDTH
PAGE COUNT REGISTER
Register
PAGE_CNT0
PAGE_CNT1
PAGE_CNTn
Reserved
PAGE_COUNT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-28
Specifications and information herein are subject to change without notice.
[0]
On all read or write commands through map 01, if this bit is
set, the data in the spare area of memory will be transferred to
the asynchronous FIFO of the memory controller along with
the main data. Size of the spare area is part dependent
depending on the # of sectors.
• 0 =Transfer data only.
• 1 = Increase sector size. The main data area for the page
will be transferred first and then the spare area.
Address
R/W
0x70100160
R/W Bank0 DBS_DFS width Register
0x70180160
Bit
[31:2]
[1:0]
Sets the DBS and DFS width. The default value is 0. Set by
software during initialization. Ignored if not relevant.
Address
R/W
0x70100170
R
Bank0 Page Count Register
0x70180170
Bit
[31:8]
[7:0]
Holds the copy-backed page count by multi-page copy-back
command currently being executed. Read-Only.
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Description
0
Reset Value
0x0000
Initial State
0
0
Reset Value
0x0000
Initial State
0
0
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