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TV SCALER
MODE Control Register
Register
MODE
MODE
ExtFIFOIn
CLKVALUP
CLKVAL_F
[29:24]
CLKDIR
CLKSEL_F
[22:21]
OutYCbCrFormat
[20:19]
OutRGB
DST420
R2YSel
InYCbCrFormat_
MSB
Preliminary product information describe products that are in development,
16-18
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Address
R/W
0x76300000
R/W
Bit
[31]
In FIFO Mode Enable. 1 for FIFO mode and 0 for DMA mode
[30]
Select CLKVAL_F update timing control
0 = always
1 = start of a frame (only once per frame)
Determine the rates of TSCLK and CLKVAL[5:0]
TSCLK = Clock source / (CLKVAL+1) where CLKVAL >= 1
Note. The maximum frequency of VCLK is 66MHz.
[23]
Select the clock source as direct or divide using CLKVAL_F
register
0 = Direct clock (frequency of TSCLK = frequency of Clock source)
1 = Divided by CLKVAL_F
Select the Video Clock source
00 = HCLK
01 = PLL Ext Clock input
10 = reserved
11 = 27MHz Ext Clock input
It determines the byte organization of word data when the
destination image is interleaved YCbCr format. For more
information refer to Fig.16-2(b) .
[18]
It indicates the output color space of destination image. 0 for
YCbCr or 1 for RGB.
[17]
0 for YCbCr422 and 1 for YCbCr420 destination format. It is valid
only for YCbCr destination image (i.e. OutRGB = 0)
[16]
Select color space conversion equation from RGB to YCbCr. 1 for
YCbCr Wide range and 0 for YCbCr Narrow range.
[15]
It determines the MSB of byte organization of word data when the
source image is interleaved YCbCr format. For more information
refer to Fig.16-2(b).
S3C6400X RISC MICROPROCESSOR
Description
Mode Register [31:0]
Description
Reset Value
0x00070B12
Initial State
0
0
0
0
0
0
1
1
1
0
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