Samsung S3C6400X User Manual page 971

SPI CONTROLLER
SIGNAL DESCRIPTIONS
The following table lists the external signals between the SPI and external device. All ports of the SPI can
be used as General Purpose I/O ports when disable. For more information refer to "General Purpose I/O"
chapter.
Name Direction
XspiCLK Inout
XspiMISO Inout
XspiMOSI Inout
XspiCS Inout
OPERATION
The SPI in S3C6400x transfers 1-bit serial data between S3C6400x and external device. The SPI in S3C6400x
supports the CPU or DMA to transmit or receive FIFOs separately and to transfer data in both directions
simultaneously. SPI has 2 channel, TX channel and RX channel. TX channel has the path from Tx FIFO to
external device. RX channel has the path from external device to RX FIFO.
CPU (or DMA) must write data on the register SPI_TX_DATA, to write data in FIFO. Data on the register are
automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU (or DMA) must access the register
SPI_RX_DATA and then data are automatically sent to the register SPI_RX_DATA.
OPERATION MODE
HS_SPI has 2 modes, master and slave mode. In master mode, HS_SPICLK is generated and transmitted to
external device. PSS, which is the signal to select slave, indicates data valid when it is low level. PSS must be set
low before packets starts to be transmitted or received.
FIFO ACCESS
The SPI in S3C6400x supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA
access to FIFOs can be selected either from 8-bit or 32-bit data. If 8-bit data size is selected, valid bits are from 0
bit to 7 bit. CPU accesses are normally on and off by trigger threshold which is user defined. The trigger level of
each FIFOs is set from 0byte to 64bytes. TxDMAOn or RxDMAOn bit of SPI_MODE_CFG register must be set to
use DMA access. DMA access supports only single transfer and 4-burst transfer. In TX FIFO, DMA request signal
is high until that FIFO is full. In RX FIFO, DMA request signal is high if FIFO is not empty.
TRAILING BYTES IN THE RX FIFO
When the number of samples in Rx FIFO is less than the threshold value in INT mode or DMA 4 burst mode and
no additional data is received, the remaining bytes are called trailing bytes. To remove these bytes in RX FIFO,
internal timer and interrupt signal are used. The value of internal timer can be set up to 1024 clocks based on
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
29-2
Specifications and information herein are subject to change without notice.
XspiCLK is the serial clock used to control time to transfer data.
In Master mode, this port is the input port. Input mode is used to get data from slave
output port. Data are transmitted to master through this port in slave mode.
In Master mode, this port is the output port. This port is used to transfer data from
master output port. Data are received from master through this port in slave mode.
Slave selection signal, all data TX/RX sequences are executed when XspiCS is low.
Table 29-1. External signals description
S3C6400X RISC MICROPROCESSOR
Description