Samsung S3C6400X User Manual page 198

S3C6400X RISC MICROPROCESSOR
UDMA Mode
Direct mode and Indirect mode
Host can control device through EBI in indirect mode. If the IO voltage of external memory is not 3.3V,
level shifter is required for data bus. Level shifter requires a direction control bit for data bus. Two pins,
XhiIRQn or XirSDBW, can be selected for a direction control bit. (These two pins are used as a control bit
not only in UDMA mode but also in PC-CARD mode and PIO mode.) CF card or micro-drive can be
connected directly to S3C6400 in direct mode without any extra work.
UDMA-In Transfer (termination by device)
DMARQ
DMACK
DIOW
DIOR
CS0,CS1,
DA[2:0]
IORDY
RD
DD[15:0 ] or
DD[7:0]
UDMA-In Transfer (termination by host)
DMARQ
DMACK
DIOW
DIOR
CS0,CS1,
DA[2:0]
IORDY
RD
DD[15:0 ] or
DD[7:0]
tACKENV tACKENV
Figure 5-6: UDMA - In operation (terminated by device)
tRP
Figure 9-7: UDMA - In Operation (terminated by host)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
tACKENV
tACKENV
tDVS
CF CONTROLLER
tACKENV
tDVS tDVH
CRC
tACKENV
tDVH
9-11