Samsung S3C6400X User Manual page 100

MEMORY SUBSYSTEM
When NAND Flash or OneNAND is selected for boot device, nCS2 is used to access that boot media.
EBI module supports AMBA AXI 3.0 low power interface (CSYSREQ, CACTIVE, and CSYSACK) to prevent
memory controllers from accessing memories.
Data pin [31:16] of memory port 1 can be used as Address pin [31:16] of memory port 0 by configuration from
system controller.
EBI module supports the share of pad interface used by 6 memory controllers. (DMC0, SROMC, two
OneNANDC, CFCON, NFCON)
Pad interface ownership is determined by priority that can be changed.
The handshaking between the EBI and the memory controller consists of a three-wire interface, EBIREQ,
EBIGNT, and EBIBACKOFF, all active HIGH :
EBIREQ signals are asserted by memory controllers to indicate that they require external bus access.
The respective arbitrated EBIGNT is issued to the highest priority memory controller.
EBIBACKOFF is output by the EBI to signal that the memory controller must complete the current transfer
and release the bus.
The EBI arbitration scheme keeps track of the memory controller that is currently granted and waits for the
transaction from that memory controller to finish (EBIREQ taken LOW by the memory controller) before it
grants the next memory controller. If a higher priority memory controller requests the bus then EBIBACKOFF
signals the currently granted memory controller to terminate the current transfer as soon as possible.
EBI
DMC0
SROMC
OneNANDC
NFCON
CFCON
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
4-2
Specifications and information herein are subject to change without notice.
MUX
Figure 4-1. EBI Block Diagram
S3C6400X RISC MICROPROCESSOR
FSM
Busreq_in0,
Busreq_in1,
Busreq_in2,
Busreq_in3,
Busreq_in4,
Busreq_in5
ACK_out0,
ACK_out1,
ACK_out2,
ACK_out3,
ACK_out4,
ACK_out5
BACKOFF_out0,
BACKOFF_out1,
BACKOFF_out2,
BACKOFF_out3,
BACKOFF_out4,
BACKOFF_out5