Samsung S3C6400X User Manual page 116

DRAM CONTROLLER
CAS Half cycle [0]
T_DQSS REGISTER
Register
P0T_DQSS 0x7E000018
P1T_DQSS 0x7E001018
PnT_DQSS Bit
[31:2]
t_DQSS [1:0]
T_MRD REGISTER
Register
P0T_MRD 0x7E00001C
P1T_MRD 0x7E00101C
PnT_MRD Bit
[31:7]
t_MRD [6:0]
T_RAS REGISTER
Register
P0T_RAS 0x7E000020
P1T_RAS 0x7E001020
PnT_RAS Bit
[31:4]
t_RAS [3:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-10
Specifications and information herein are subject to change without notice.
Encodes whether the CAS latency is half a memory clock cycle
more than the value given in bits[3:1]
0 = Zero cycle offset to value in [3:1]. [0] is forced to 0 in MDDR
and SDR mode.
1 = Half cycle offset to the value in [3:1].
Address R/W
R/W
R/W
Read undefined. Write as Zero
Write to DQS in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set mode register command time in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set RAS to precharge delay in memory clock cycles.
Description
16-bit DRAM controller t_DQSS register
32-bit DRAM controller t_DQSS register
Description
Description
16-bit DRAM controller t_MRD register
32-bit DRAM controller t_MRD register
Description
Description
16-bit DRAM controller t_RAS register
32-bit DRAM controller t_RAS register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
Initial State
Reset Value
Initial State
Reset Value
Initial State
0
0x1
0x1
1
0x02
0x02
0x02
0x7
0x7
0x7