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HOST INTERFACE
CPUIF CLIENT CONTROL REGISTER (CPUIFC_CTRL)
Offset=0x00, R/W, Reset Value=0x20FF_0100
Field
Reserved
INV_INTR
Reserved
Reserved
Reserved
Reserved
CPUIF Client Temporary Register (CPUIFC_TMP)
Offset=0x08, R/W, Reset Value=0x0000_0000
Field
DATA
CPUIF IMB Register (CPUIFC_IMB)
Offset=0x10, R, Reset Value=0x0000_0000
Field
IMB
CPUIF OMB Register (CPUIFC_OMB)
Offset=0x14, R/W, Reset Value=0x0000_0000
Field
OMB
24-22
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit
[31:30]
Reserved
[29]
Polarity inversion of INTR
0: INTR is active high so that INTR becomes HIGH when an
interrupt occurs.
1: INTR is active low so that INTR becomes LOW when an
interrupt occurs.
Note: "INV_INTR" field of the HOST I/F block and
"INT2M_LEVEL" of the MODEM I/F block must have same
polarity.
[28:24]
Reserved
[23:16]
Reserved
[15:9]
Reserved
[8:0]
Reserved
Bit
[31:0]
Temporary register
This register can be used for the design revision or the
verification.
Bit
[31:0]
A 32-bit In-MailBox Shadow register
Bit
[31:0]
A 32-bit Out-MailBox register
S3C6400X
Description
Description
Description
Description
RISC MICROPROCESSOR
Initial State
0
1
0x0
0xFF
0x0
0x100
Initial State
0x0000_0000
Initial State
0x0000_0000
Initial State
0x0000_0000
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