Samsung S3C6400X User Manual page 735

FIMV-MFC V1.0
VC1_DEC VC1_DEC_DEBLK
According to the requirements of target application, application could reserve Work Buffer space by selecting the
sub-set of the buffers presented in this table.
Description of Run Process
BIT processor can execute maximum 8 processes simultaneously. Each process may have different Codec
Standard (MPEG4 DECODE, H.264 ENCODE, etc.). Each process has different bit stream buffer and related
read/write pointer register (BitStreamRdPtr0, BitStreamWrPtr0, etc.). The process is generated by
DEC_SEQ_INIT/ENC_SEQ_INIT command and terminated by DEC_SEQ_END/ENC_SEQ_END command.
Each process is identified with RunIndex register at executing command. Bit processor schedules every process
by host executing command (picture by picture basis). Switching to different process requires a little
cycle/bandwidth overhead for context switching of BIT processor. At each context switching about 8 KB data
memory of each process is read from and written to SDRAM and additional 8 KB code memory is read from
SDRAM if codec standard is different between previous and current process. Therefore worst-case context
switching overhead SDRAM bandwidth is about {8KB(R)+ 8KB(W) + 8KB(R)} * 30 Hz * 8 process = 5760 KB / sec
(at 30 frame / sec).
BIT processor requires about 0.75 cycles / byte for reading or writing SDRAM data at burst mode. Therefore worst
case context switching overhead cycles are about {8K + 8K + 8K} * 0.75 * 30 Hz * 8 process ~= 4.4 M Cycles
Description of Pre/Post Rotation
Encoding source image may be rotated prior to encoding process (pre-rotation) and decoded output image may
be rotated after decoding process. Host may inform the pre/post rotation mode at every encoding/decoding a
picture.
In pre-rotation case, the rotation is performed at reading source image process. Therefore no further SDRAM
bandwidth is needed for pre-rotation. After reading the rotated source image, remaining encoding process is
same with no pre-rotation case.
In post-rotation case, the rotation is performed at storing decoded image process. But the decoded image (prior to
rotation) is used for future frame decoding for reference of motion compensation. Therefore the decoded image
must be stored when post-rotation is enabled and further SDRAM bandwidth is needed for additional post-rotated
image store.
The pre/post rotation mode is composed of 4 bit field. The first bit (most significant bit) is horizontal mirroring, the
next bit is vertical mirroring and last two bits (least significant two bits) are counterclockwise rotation degree. Each
mirroring/rotation field (horizontal, vertical, rotation) is applied independently.
Overlap/deblock filter
working buffer
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MULTI-FORMAT
VIDEO
8
CODEC
21-109