Samsung S3C6400X User Manual page 52

S3C6400X RISC MICROPROCESSOR
integer value. For example, if DIV
Otherwise, the IP's on APB bus system cannot transfer data correctly.
JPEG and security sub-system on AHB bus system cannot be running at 133MHz.AHB clocks are independently
generated with DIV
CLKJPEG
operating frequency ratio must be even number (DIV
and CLK_DIV0[19:18], respectively).
Table 3-2 shows the recommended clock divider ratio.
Table 3-2. Typical value setting for clock dividers (SFR setting value / output frequency)
APLL MPLL
266MHz 266MHz
400MHz 266MHz
533MHz 266MHz
667MHz 266MHz
The divider for ARM independently uses the output clock of APLL and there is no constraint for clock divider value
as shown in the above table.
Clock ratio change
Clock dividers in Figure 3-2 generate various operating clocks including the system operating clocks, ARMCLK,
HCLKX2, HCLK, and PCLK. Figure 3-6 shows a transition waveform when the cock dividers for the system
operating clocks change the ratio from one to two. As shown the figure, PLL output clock will be slow during ratio
changing period. This period is not fixed and approximately 10~20 clock cycles in typical case.
Therefore, if some IP runs with CLKCAM, CLKMFC, DOUT
required for this ratio-changing period. Otherwise, IPs may be failed to operate.
has 1 of CLK_DIV0[8], then DIV
HCLK
and DIV . Therefore, they have same constraints as APB clock, i.e., the
CLKSECUR
DIV
DIV
ARM HCLKX2
0 / 266MHz 0 / 266MHz
0 / 400MHz 0 / 266MHz
0 / 533MHz 0 / 266MHz
0 / 667MHz 0 / 266MHz
Figure 3-6. Waveform during system clock ratio is changing.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
must be 1, 3, ... of CLK_DIV0[15:12].
PCLK
and DIV
CLKJPEG CLKSECUR
DIV DIV
HCLK PCLK
1 / 133MHz 3 / 66MHz
1 / 133MHz 3 / 66MHz
1 / 133MHz 3 / 66MHz
1 / 133MHz 3 / 66MHz
as shown in Figure 3-2, special care may be
MPLL
SYSTEM CONTROLLER
must be 1, 3, ... of CLK_DIV0[27:24]
DIV DIV
CLKJPEG
3 / 66MHz 3 / 66MHz
3 / 66MHz 3 / 66MHz
3 / 66MHz 3 / 66MHz
3 / 66MHz 3 / 66MHz
CLKSECUR
3-7