Samsung S3C6400X User Manual page 74

S3C6400X RISC MICROPROCESSOR
Clock output configuration register
Internal clocks can be monitored through GPIO port, which is GPIO port-F. CLK_OUT register selects an internal
clock among PLL output, HCLK, 48MHz, 27MHz, RTC, and TICK. It also divides the selected clock.
REGISTER
CLK_OUT 0x7E00_F02C
CLK_OUT
RESERVED [31:20] RESERVED
DIVVAL [19:16]
RESERVED
CLKSEL [14:12]
DCLKCMP
DCLKDIV
RESERVED
DCLKSEL
DCLKEN
ADDRESS R/W
R/W
BIT
Divide ratio (Divide ratio = DIVVAL + 1). If this field has not
0, DCLKCMP has no meanng. Therefore, DOUT is always
50% duty ratio when DIVVAL > 0.
[15] RESERVED
000 = FOUT
APLL
001 = FOUT
EPLL
010 =HCLK
011 =CLK48M
100 =CLK27M
101 =RTC
110 =TICK
111 =DOUT
This field changes the clock duty of DCLK. Thus, it must be
smaller than DCLKDIV. It is valid only when CLKSEL is
3'b111.
[11:8]
If the DCLKCMP is n, low level duration is (n+1).
High level duration is ((DCLKDIV + 1) – (n+1))
DCLK divide value
[7:4]
DCLK frequency = source clock / (DCLKDIV + 1)
[3:2] RESERVED
[1] Select DCLK source clock (0: PCLK, 1: 48MHz)
[0] Enable DCLK (0:disable, 1:enable)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DESCRIPTION
Select clock output
DESCRIPTION
/2
SYSTEM CONTROLLER
RESET VALUE
0x0000_0000
RESET VALUE
0x000
0x0
0
0x0
0x0
0x0
0x0
0
0
3-29