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POST PROCESSOR
5. Frame Management of POST Processor
5.1 Per Frame Management Mode
Per frame management of POST-Processor are controlled by two control register such as POSTENVID and
POSTINT as shown in Figure 15-8. "POSTENVID" triggers the operation of POST PROCESSOR. It is
automatically de-asserted when all operations of the given frame are completed. Before asserting "POSTENVID",
all control registers must be set to the proper value as explained in the previous chapters. When all operations are
completed, interrupt pending register is asserted (POSTINT=1), if the interrupt enable signal is asserted
(INTEN=1). The POSTINT signal, directing to the interrupt controller, must be cleared by the interrupt service
routine. The polling POSTENVID is used to detect the end of the operation.
POSTENVID
POSTINT
Figure 15-8 Start and termination of POST PROCESSOR operation ( AutoLoadEnable = 0 ) Block
5.2 Free Run Mode
To activatethe new frame management scheme of free run operation, you must set "AutoLoadEnable" bit to 1. In
this mode, user can pre-define the next frame-related address set of NxtADDRXXX (defined in chapter 6 Register
files) even when the current frame is under operation. When the current frame is completely finished, the following
operations are executed step-by-step.
1. According to INTEN, interrupt signal is asserted or not.
2. Next frame address set of NxtADDRXXX is copied into the current frame address set of ADDRXXX.
3. ENVID is automatically asserted and the next frame operation starts up.
** In Free Run Mode, the other register value except the address stuff must remain the same value between the
current frame and the next frame.
Preliminary product information describe products that are in development,
15-14
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Users set
(Start operation)
Control Register Set
Diagram
S3C6400X RISC MICROPROCESSOR
Automatic clear/assertion
(Terminate operation)
(INTEN=1)
(INTEN=0)
User clear
if asserted
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