Samsung S3C6400X User Manual page 852

S3C6400X RISC MICROPROCESSOR
ChHltd
XferCompl
HOST CHANNEL-n INTERRUPT MASK REGISTER (HCINTMSKn)
Channel_number : 0≤ n≤ 15
This register reflects the mask for each channel status described in the previous section.
· Mask interrupt : 1'b0
· Unmask interrupt : 1'b1
Register Address
HCINTMSKn 0x7C00_050
C+n*20h
HCINTMSKn
[31:11]
DataTglErrMsk
FrmOvrunMsk
BblErrMsk
XactErrMsk
NyetMsk
AckMsk
NakMsk
StallMsk
AHBErrMsk
ChHltdMsk
XferComplMsk
HOST CHANNEL-n TRANSFER SIZE REGISTER (HCTSIZn)
Channel_number : 0≤ n≤ 15
Register Address
HCTSIZn 0x7C00_0510
+n*20h
WC This is generated only in Internal DMA mode when
there is an AHB error during AHB read/write. The
application can read the corresponding channel's
DMA address register to get the error address.
[1] R_SS_ Channel Halted
WC Indicates the transfer completed abnormally either
because of any USB transaction error or in response
to disable request by the application.
[0] R_SS_ Transfer Completed
WC Transfer completed normally without any errors.
R/W
R/W
Bit R/W
Reserved
[10] R_W Data Toggle Error Mask
[9] R_W Frame Overrun Mask
[8] R_W Babble Error Mask
[7] R_W Transaction Error Mask
[6] R_W NYET Response Received Interrupt Mask
[5] R_W ACK Response Received Interrupt Mask
[4] R_W NAK Response Received Interrupt Mask
[3] R_W STALL Response Received Interrupt Mask
[2] R_W AHB Error Mask
[1] R_W Channel Halted Mask
[0] R_W Transfer Completed Mask
R/W
R/W
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Host Channel-n interrupt Mask Register
Description
Description
Host Channel-n Transfer Size Register
USB2.0 HS OTG
1'b0
1'b0
Reset Value
32 bits
Initial State
21'h0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
Reset Value
32 bits
26-45