Samsung S3C6400X User Manual page 1011

UART
Note:
1) DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16. Refer to UART Buad Rate Configure Registers.
2) S3C6400 is using a level-triggered interrupt controller. Therefore, these bits must be set to 1 for every transfer.
3) When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA
receive mode with FIFO, the Rx interrupt will be generated (receive time out), and the you must check the FIFO
status and read out the rest.
4) EXT_UCLK0 clock is external clock.(XpwmECLK PAD input)
EXT_UCLK1 clock is generated clock by SYSCON. SYSCON generates EXT_UCLK1 for dividing EPLL or
MPLL output.
31-16
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
S3C6400 RISC MICROPROCESSOR