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ONENAND CONTROLLER
MEMORY RESET REGISTER
Register
MEM_RESET0
MEM_RESET1
MEM_RESETn
Reserved
RESET_CODE
INTERRUPT ERROR STATUS REGISTER
Register
INT_ERR_STAT0
INT_ERR_STAT1
INT_ERR_STATn
Reserved
CACHE_OP_ERR
RST_CMP
RDY_ACT
INT_ACT
UNSUP_CMD
LOCKED_BLK
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-20
Specifications and information herein are subject to change without notice.
4: Supports SINGLE and INCR4.
8: Supports SINGLE and INCR4.
16: Supports SINGLE, INCR4 and INCR8.
Others: Reserved
Address
R/W
0x70100020
R/W Bank0 Memory Reset Register
0x70180020
Bit
[31:3]
[2:0]
Sets the reset code. This register will reset to 0x0 after the
reset sequence has been completed. This register is
controlled through software.
• 001 = Warm Reset.
• 010 = Core Reset.
• 011 = Hot Reset.
• All other settings Reserved.
Address
R/W
0x70100030
R/W Bank0 Interrupt Error Status Register
0x70180030
Bit
[31:14]
[13]
An error occurred during a cache read or write setup or
operation.
[12]
The controller has completed its reset and initialization
process. Be sure to check whether this bit is one before
OneNAND access is executed.
[11]
The memory device's RDY pin is actively transitioning.
[10]
The memory device's INT pin is actively transitioning.
[9]
An unsupported command was received. This interrupt is set
when an invalid command is received, or when a command
sequence is broken.
[8]
The address to program or erase is in a protected block.
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Description
Reset Value
0x0000
Initial State
0
0
Reset Value
0x0000
Initial State
0
0
0
0
0
0
0
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