Samsung S5PC110 Manuals

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Samsung S5PC110 Manual

Samsung S5PC110 Manual (2426 pages)

RISC Microprocessor

Brand: Samsung | Category: Computer Hardware | Size: 32.14 MB

Table of Contents

Section 1

5
- Important Notice
  2
- Revision History
  3
- Table of Contents
  5
- 1 Overview of S5PC110
  
  7
  - Architectural Overview
    7
  - Block Diagram of S5PC110
    8
  - Key Features of S5PC110
    9
    
    Microprocessor
    10
    
    Memory Subsystem
    11
    
    Multimedia
    12
    
    Audio Subsystem
    15
    
    Security Subsystem
    15
    
    Connectivity
    16
    
    System Peripheral
    19
  - Conventions
    21
    
    Register R/W Conventions
    21
    
    Register Value Conventions
    21
- 2 Memory Map
  
  22
  - Memory Address Map
    22
    
    Device Specific Address Space
    23
    
    Special Function Register Map
    25
Section 2

29
- 1 Chip ID
  
  35
  - Overview of CHIP ID
    35
  - Register Description
    36
    
    Register Map
    36
- 2 General Purpose Input/ Output
  
  37
  - Overview
    37
    
    Features
    38
    
    Input/ Output Configuration
    38
    
    S5PC110 Input/ Output Types
    38
    
    IO Driver Strength
    39
    
    Input/ Output Description
    43
  - Register Description
    60
    
    Register Map
    60
    
    Port Group GPA0 Control Register
    78
    
    Port Group GPA1 Control Register
    80
    
    Port Group GPB Control Register
    82
    
    Port Group GPC0 Control Register
    84
    
    Port Group GPC1 Control Register
    86
    
    Port Group GPD0 Control Register
    88
    
    Port Group GPD1 Control Register
    90
    
    Port Group GPE0 Control Register
    92
    
    Port Group GPE1 Control Register
    94
    
    Port Group GPF0 Control Register
    96
    
    Port Group GPF1 Control Register
    99
    
    Port Group GPF2 Control Register
    102
    
    Port Group GPF3 Control Register
    105
    
    Port Group GPG0 Control Register
    107
    
    Port Group GPG1 Control Register
    109
    
    Port Group GPG2 Control Register
    111
    
    Port Group GPG3 Control Register
    113
    
    Port Group GPI Control Register
    115
    
    Port Group GPJ0 Control Register
    117
    
    Port Group GPJ1 Control Register
    120
    
    Port Group GPJ2 Control Register
    122
    
    Port Group GPJ3 Control Register
    125
    
    Port Group GPJ4 Control Register
    128
    
    Port Group MP0_1 Control Register
    130
    
    Port Group MP0_2 Control Register
    132
    
    Port Group MP0_3 Control Register
    134
    
    Port Group MP0_4 Control Register
    137
    
    Port Group MP0_5 Control Register
    139
    
    Port Group MP0_6 Control Register
    141
    
    Port Group MP0_7 Control Register
    143
    
    Port Group MP1_0 Control Register
    145
    
    Port Group MP1_1 Control Register
    145
    
    Port Group MP1_2 Control Register
    146
    
    Port Group MP1_3 Control Register
    146
    
    Port Group MP1_4 Control Register
    147
    
    Port Group MP1_5 Control Register
    147
    
    Port Group MP1_6 Control Register
    148
    
    Port Group MP1_7 Control Register
    148
    
    Port Group MP1_8 Control Register
    149
    
    Port Group MP2_0 Control Register
    149
    
    Port Group MP2_1 Control Register
    150
    
    Port Group MP2_2 Control Register
    150
    
    Port Group MP2_3 Control Register
    151
    
    Port Group MP2_4 Control Register
    151
    
    Port Group MP2_5 Control Register
    152
    
    Port Group MP2_6 Control Register
    152
    
    Port Group MP2_7 Control Register
    153
    
    Port Group MP2_8 Control Register
    153
    
    Port Group ETC0 Control Register
    154
    
    Port Group ETC1 Control Register
    155
    
    Port Group ETC2 Control Register
    157
    
    Port Group ETC3 Is Reserved
    159
    
    Port Group ETC4
    159
    
    GPIO Interrupt Control Registers
    232
    
    Port Group GPH0 Control Register
    269
    
    Port Group GPH1 Control Register
    271
    
    Port Group GPH2 Control Register
    273
    
    Port Group GPH3 Control Register
    275
    
    External Interrupt Control Registers
    277
    
    Extern Pin Configuration Registers in Power down Mode
    297
- 3 Clock Controller
  
  298
  - Clock Domains
    298
  - Clock Declaration
    299
    
    Clocks from Clock Pads
    299
    
    Clocks from CMU
    300
  - Clock Relationship
    301
    
    Recommended PLL PMS Value for APLL
    302
    
    Recommended PLL PMS Value for EPLL
    303
    
    Recommended PLL PMS Value for MPLL
    303
    
    Recommended PLL PMS Value for VPLL
    304
  - Clock Generation
    305
  - Table 3-5 Maximum Operating Frequency for each Sub-Block
    307
  - Clock Configuration Procedure
    308
    
    Clock Gating
    308
  - Special Clock Description
    309
    
    Special Clock Table
    309
    
    Table 3-7 I/O Clocks in S5PC110
    310
  - Register Description
    311
    
    Register Map
    311
    
    PLL Control Registers
    315
    
    Clock Source Control Registers
    322
    
    Clock Divider Control Register
    331
    
    Clock Gating Control Register
    336
    
    Clock Output Configuration Register
    348
    
    Figure 3-4 CLKOUT Waveform with DCLK Divider
    349
    
    Clock Divider Status Sfrs
    350
    
    Clock MUX Status Sfrs
    352
    
    IEM Control Sfrs
    354
    
    Other Sfrs
    354
    
    Miscellaneous Sfrs
    360
- 4 Power Management
  
  361
  - Overview of PMU
    361
  - Functional Description of PMU
    362
  - Table 4-2 S5PC110 Power Domains of Internal Logic
    363
  - System Power Mode
    364
    
    Overview
    364
    
    Normal Mode
    367
    
    DEEP-IDLE Mode
    369
    
    IDLE Mode
    369
    
    STOP Mode
    371
    
    DEEP-STOP Mode
    373
    
    SLEEP Mode
    375
  - System Power Mode Transition
    377
    
    Figure 4-2 Internal Operation During Power Mode Transition
    378
    
    Transition Entering/ Exiting Condition
    379
  - Cortex-A8 Power Mode
    381
    
    Cortex-A8 Power Mode Transition
    381
    
    Overview
    381
    
    Figure 4-3 Cortex-A8 Power Mode Transition Diagram
    382
    
    State Save and Restore
    384
  - Wakeup Sources
    385
    
    External Interrupts
    385
    
    RTC Alarm
    385
    
    System Timer
    385
  - External Power Control
    386
    
    Hdmi Phy
    387
    
    Usb Otg Phy
    387
    
    Mipi D-Phy
    388
    
    Pll
    388
    
    Dac
    389
    
    Table 4-8 the Status of MPLL and SYSCLK after Wake-Up
    389
    
    Adc I/O
    390
    
    Por
    390
  - Internal Memory Control
    391
    
    Sram
    391
    
    Rom
    392
  - Reset Control
    393
    
    Hardware Reset
    393
    
    Reset Types
    393
    
    Table 4-10 Register Initialization Due to Various Resets
    397
  - Register Description
    398
    
    Register Map
    398
    
    Clock Control Register
    400
    
    Reset Control Register
    401
    
    Power Management Register
    402
    
    MISC Register
    413
- 5 Intelligent Energy Management
  
  418
  - Overview of Intelligent Energy Management
    418
    
    Key Features of Intelligent Energy Management
    419
    
    Block Diagram
    420
  - Functional Description of Intelligent Energy Management
    421
    
    IEM System Components
    421
    
    IEM System Operation
    426
  - IEM Implementation and Driver Setting
    430
    
    Definition of Performance
    430
    
    HPM Structure and Closed-Loop Behavior
    431
    
    Figure 5-5 IEM Closed-Loop Control Flow in APC1 HPM Delay
    432
    
    Figure 5-6 HPM Delay Tap Structure in S5PC110
    433
    
    Initialization Sequence
    434
  - I/O Description
    435
  - Register Description
    436
    
    Register Map
    436
    
    IEC Related Registers
    439
    
    APC1 Related Registers
    451
- 6 Booting Sequence
  
  464
  - Overview of Booting Sequence
    464
  - Figure 6-1 Block Diagram of Booting Time Operation
    465
  - Scenario Description
    466
    
    Reset Status
    466
    
    Booting Sequence Example
    467
    
    Fixed PLL and Clock Setting
    469
    
    OM Pin Configuration
    470
    
    Secure Booting
    472
    
    Figure 6-3 Secure Booting Diagram
    473
Section 3

475
- 1 Bus Configuration
  
  478
  - Overview of Bus Configuration
    478
    
    AXI Interconnect
    478
  - Register Description
    482
    
    Register Map
    482
    
    Synchronizer Configuration Register (ASYNC_CONFIG0~10, R/W)
    483
- 2 Coresight
  
  484
  - Coresight System Overview
    484
    
    About Coresight Systems Generals
    484
    
    Key Features of Coresight
    485
  - Debug Access Port
    490
    
    About Debug Access Port
    490
  - Etb
    492
    
    About the ETB
    492
    
    About the ECT
    493
- 3 Access Controller (TZPC)
  
  494
  - Overview of Access Controller (TZPC)
    494
    
    Block Diagram of Access Controller (TZPC)
    494
    
    Key Features of Access Controller (TZPC)
    494
  - Functional Description
    495
  - TZPC Configuration
    496
  - Register Discription
    498
    
    Register Map
    498
Section 4

507
- Vectored Interrupt Controller
  508
  - Overview of Vectored Interrupt Controller
    508
    
    Key Features of Vectored Interrupt Controller
    508
  - Nterrupt Source
    509
  - Functional Description
    513
  - Register Description
    514
    
    Register Map
    514
Section 5

538
- 1 DRAM Controller
  
  544
  - Overview of DRAM Controller
    544
    
    Introduction of DRAM Controller
    544
    
    Key Features of DRAM Controller
    544
    
    Supports Clock Frequency up to 200Mhz Block Diagram
    545
  - Functional Description
    546
    
    Initialization
    546
    
    Address Mapping
    549
    
    Low Power Operation
    551
    
    Precharge Policy
    552
    
    Quality of Service
    554
    
    Read Data Capture
    557
  - I/O Description
    562
    
    PAD Mux for Address Configuration
    563
  - Register Description
    564
    
    Register Map
    564
- 2 SROM Controller
  
  593
  - Overview of SROM Controller
    593
  - Key Features of SROM Controller
    593
  - Block Diagram of SROM Controller
    593
  - Functional Description
    594
    
    Nwait Pin Operation
    594
    
    Programmable Access Cycle
    595
  - I/O Description
    596
  - Register Description
    597
    
    Register Map
    597
- 3 Onenand Controller
  
  603
  - Overview of Onenand Controller
    603
  - Key Features of Onenand Controller
    603
  - Controller Usage Expectations
    604
  - Functional Description of Onenand
    605
    
    Block Diagram of Oneenand Controller
    605
    
    Clock Control
    606
    
    Initialization Protocol
    606
  - Memory Map
    607
  - Onenand Interface
    613
    
    Overview of Onenand Interface
    613
    
    Onenand Interface Configuration
    614
    
    Onenand Device Interrupt Handling
    617
    
    DMA Engine Overview
    620
    
    DMA Operation
    621
  - I/O Interface
    623
  - Register Description
    624
    
    Register Map
    624
    
    Onenand Interface Register
    625
    
    DMA Control Registers
    632
    
    Interrupt Controller Registers
    638
- 4 NAND Flash Controller
  
  642
  - Overview of NAND Flash Controller
    642
  - Key Features of NAND Flash Controller
    642
    
    Block Diagram
    643
    
    NAND Flash Memory Timing
    643
  - Software Mode
    645
    
    Data Register Configuration
    645
    
    4-/ 8-/ 12-/ 16-Bit ECC
    646
    
    1-Bit ECC Module Features
    647
    
    Byte 1-Bit ECC Parity Code Assignment Table
    647
    
    1-Bit ECC Programming Guide
    648
    
    4-Bit ECC Programming Guide (ENCODING)
    649
    
    4-Bit ECC Programming Guide (DECODING)
    650
    
    8-Bit / 12-Bit / 16-Bit ECC Programming Guide (ENCODING)
    651
    
    8/12/16-Bit ECC Programming Guide (DECODING)
    652
    
    ECC Parity Conversion Code Guide for 8/12/16-Bit ECC
    653
    
    Lock Scheme for Data Protection
    654
  - I/O Description
    655
  - Register Description
    656
    
    Register Map
    656
    
    Nand Flash Interface and 1 / 4-Bit Ecc Registers
    658
    
    ECC Registers for 8, 12 and 16-Bit Ecc
    667
- 5 Compact Flash Controller
  
  673
- 6 External Bus Interface
  
  700
Section 6

704
- DMA Controller
  707
- Overview of DMA Controller
  707
  - Key Features of DMA Controller
    708
- Register Description
  711
  - Register Map
    711
- Instruction
  731
  - Key Instruction
    732
  - USAGE Model
    734
Section 7

738
- 1 Pulse Width Modulation Timer
  
  742
  - Overview of Pulse Width Modulation Timer
    742
  - Key Features of Pulse Width Modulation Timer
    745
  - PWM Operation
    746
    
    Basic Timer Operation
    746
    
    Prescaler and Divider
    746
    
    Auto-Reload and Double Buffering
    748
    
    Timer Operation Example
    749
    
    Initialize Timer (Setting Manual-Up Data and Inverter)
    750
    
    PWM (Pulse Width Modulation)
    750
    
    Output Level Control
    751
    
    Dead Zone Generator
    752
  - I/O Description
    753
  - Register Description
    754
    
    Register Map
    754
- 2 System Timer
  
  761
  - Overview of System Timer
    761
  - Key Features of System Timer
    762
  - Internal Function of System Timer
    762
  - Detailed Operation
    763
  - Tick Generation with Fractional Divider
    764
  - Usage Model
    766
    
    Count Value Update
    766
    
    Counter Setting
    766
    
    Interrupt
    766
    
    Change Interval Interrupt at Run-Time
    767
    
    START Timer
    767
    
    STOP Timer
    767
  - I/O Description
    768
  - Register Description
    769
    
    Register Map
    769
- 3 Watchdog Timer
  
  774
  - Overview of Watchdog Timer
    774
  - Key Features of Watchdog Timer
    774
  - Functional Description of Watchdog Timer
    775
    
    Watchdog Timer Operation
    775
    
    WDT Start
    775
    
    WTDAT and WTCNT
    775
    
    Consideration of Debugging Environment
    776
  - Register Description
    777
    
    Register Map
    777
- 4 Real Time Clock (RTC)
  
  780
Section 8

796
- 1 Universal Asynchronous Receiver and Transmitter
  
  803
  - Overview of Universal Asynchronous Receiver and Transmitter
    803
  - KEY Features of Universal Asynchronous Receiver and Transmitter
    803
  - UART Description
    805
    
    Auto Flow Control (AFC)
    805
    
    Data Reception
    805
    
    Data Transmission
    805
    
    Example of Non Auto-Flow Control (Controlling Nrts and Ncts by Software)
    806
    
    Interrupt/Dma Request Generation
    807
    
    RS-232C Interface
    807
    
    Tx/Rx FIFO Trigger Level and DMA Burst Size in DMA Mode
    807
    
    UART Error Status FIFO
    808
  - UART Input Clock Diagram Description
    812
  - I/O Description
    813
  - Register Description
    814
    
    Register Map
    814
- 2 IIC-Bus Interface
  
  833
  - Overview of IIC-Bus Interface
    833
  - Key Features of IIC-Bus Inteface
    834
  - I I C-Bus Interface Operation
    835
    
    Start and Stop Conditions
    835
    
    Data Transfer Format
    836
    
    ACK Signal Transmission
    837
    
    Abort Conditions
    838
    
    Bus Arbitration Procedures
    838
    
    Configuring I I C-Bus
    838
    
    Read-Write Operation
    838
    
    Flowcharts of Operations in each Mode
    839
  - I/O Description
    843
  - Register Description
    844
    
    Register Map
    844
- 3 Serial Peripheral Interface
  
  849
  - Overview of Serial Peripheral Interface
    849
  - Key Features of Serial Peripheral Interface
    849
    
    Operation of Serial Peripheral Interface
    850
  - IO Description
    853
  - Register Description
    854
    
    Register Map
    854
    
    Special Function Register
    857
- 4 USB 2.0 Host Controller
  
  867
Section 9

1101
- 1 Display Controller
  
  1112
  - Overview of Display Controller
    1112
  - Key Features of the Display Controller
    1113
  - Functional Description of Display Controller
    1115
    
    Brief Description of the Sub-Block
    1115
    
    Data Flow
    1115
    
    Overview of the Color Data
    1118
    
    Color Space Conversion (CSC)
    1133
    
    Palette Usage
    1135
    
    Window Blending
    1137
    
    Image Enhancement
    1146
    
    VTIME Controller Operation
    1151
    
    Setting of Commands
    1153
    
    Virtual Display
    1156
    
    RGB Interface Spec
    1157
    
    LCD Indirect I80 System Interface
    1164
  - Programmer's Model
    1168
    
    Overview of Programmer's Model
    1168
  - Register Description
    1169
    
    Register Map
    1169
    
    Palette Memory (Palram)
    1177
    
    Gamma LUT Data
    1245
- 2 Camera Interface
  
  1248
  - Overview of Camera Interface
    1248
  - Key Features of CAMIF
    1250
  - External Interface
    1252
  - Input/ Output Description
    1253
  - Timing Diagram and Data Alignment of Camera
    1254
    
    Timing Diagram of ITU Camera
    1254
    
    MIPI CSI Data Alignment from MIPI Camera
    1257
  - External Connection Guide
    1258
  - Camera Interface Operation
    1259
    
    Input/ Output DMA Ports
    1259
    
    Clock Domain
    1260
    
    Frame Memory Hierarchy
    1261
    
    Memory Storing Method
    1262
    
    Timing Diagram for Register Setting
    1263
    
    Timing Diagram for Last IRQ
    1265
    
    Timing Diagram for IRQ (Memory Data Scaling Mode)
    1266
    
    Input DMA Feature
    1267
    
    Camera Interlace Input Support
    1268
  - Register Description
    1269
    
    Register Map
    1269
    
    Register Seting Guide for Scaler
    1293
- 3 Mipi Dsim
  
  1335
  - Data Format
    1371
  - Hardware Overview
    1397
  - Video Dac
    1532
Section 10

1799
- 1 Audio Subsystem
  
  1805
  - Overview of the Audio Subsystem
    1805
  - Key Features of Audio Subsystem
    1805
  - Input/ Output Description
    1806
  - Block Diagram of Audio Subsystem
    1807
  - Functional Description
    1809
    
    Ass Clk con
    1809
    
    Commbox
    1809
    
    Reconfigurable Processor
    1809
    
    I2S_V51
    1810
    
    Sram
    1810
  - Register Description
    1811
    
    Register Map
    1811
    
    Audio Subsystem CLK con
    1813
    
    Commbox
    1815
- 2 IIS Multi Audio Interface
  
  1818
  - Overview of IIS Multi Audio Interface
    1818
  - Key Features of IIS Multi Audio Interface
    1818
  - Block Diagram of IIS Multi Audio Interface
    1819
  - Functional Descriptions
    1820
    
    Master/Slave Mode
    1820
  - Audio Serial Data Format
    1825
    
    IIS-Bus Format
    1825
    
    MSB (Left) Justified
    1825
    
    LSB (Right) Justified
    1826
  - PCM BIT Length (BLC), RFS Divider and BFS Divider for Sampling Frequency (Iislrclk), SERIAL
    1827
    
    BFS Divider and RFS Divider
    1827
    
    PCM Word Length and BFS Divider
    1827
    
    RFS Divider and ROOT Clock
    1828
  - Programming Guide
    1829
    
    Initialization
    1829
    
    Play Mode (TX Mode) with DMA
    1829
    
    Recording Mode (RX Mode) with DMA
    1829
    
    Example Code
    1830
  - IO Description
    1836
  - Register Description
    1837
    
    Register Map
    1837
- 3 IIS-Bus Interface
  
  1852
  - Overview of IIS-Bus Interface
    1852
  - Key Features of IIS-Bus Interface
    1852
  - Block Diagram of IIS-Bus Interface
    1853
  - Functional Descriptions
    1854
    
    Master/Slave Mode
    1854
    
    DMA Transfer
    1855
Section 11

1952
- 1 Security-System
  
  1955
  - Overview of Security-System
    1955
- 2 Advanced Crypto Engine
  
  1956
  - Overview of Advanced Crypto Engine
    1956
    
    KEY Features of SSS
    1958
  - Functional Description of SSS
    1959
    
    CPU Mode
    1959
    
    FIFO Mode
    1959
    
    Byte Swapping Options
    1963
  - Register Description
    1966
    
    Register Map
    1966
    
    TDES Control (TDES_OUTPUT_0, R, Address = 0Xea00_5038)
    1988
Section 12

2006
- Absolute Maximum Ratings
  2009
- Electrical Data
  2009
- Recommended Operating Conditions
  2010
- Electrical Characteristics
  2013
- CLK Alternating-Current Electrical Characteristics
  2015
- ROM/ SRAM AC Electrical Characteristics
  2018
- Onenand AC Electrical Characteristics
  2020
- NFCON AC Electrical Characteristics
  2023
- LPDDR1 (Mddr) SDRAM Electrical Characteristics
  2025
- LPDDR2 Electrical Characteristi
  2027
- Modemif AC Electrical Characteristics
  2027
- LCD Controller AC Electrical Characteristics
  2028
- Camera Interface AC Electrical Characteristics
  2031
- SDMMC AC Electrical Characteristics
  2033
- SPI AC Electrical Characteristics
  2034
- I2C AC Electrical Characteristics
  2037
- TSI AC Electrical Characteristics
  2038
Section 13

2040
- 1 Type SIZE & BALL MAP
  
  2041
  - Pin Assignment
    2041
    
    Package Dimension
    2041
    
    Pin Assignment Diagram - 596-Ball FCFBGA (POP)
    2041
    
    Pin Discription
    2041
    
    Pin Number Order
    2041
    
    Power Domain
    2041
    
    Power Pins
    2041
- 2 Type SIZE & BALL MAP
  
  2045
  - Pin Assignment
    2045
    
    Pin Assignment Diagram - 596-Ball FCFBGA (POP)
    2045
    
    Power Pins
    2054
    
    Pin Discription
    2057
    
    Power Domain
    2083
    
    Package Dimension
    2098
  - Pin Assignment
    2100
    
    Power Pins
    2109
    
    Pin Discription
    2112
    
    Power Domain
    2138
    
    Package Dimension
    2152
  - Pin Assignment
    2154
    
    Power Pins
    2163
    
    Pin Discription
    2166
    
    Package Dimension
    2207
  - Pin Assignment
    2209
    
    Power Pins
    2218
    
    Pin Discription
    2221
    
    Package Dimension
    2261

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