Samsung S3C6400X User Manual page 955

S3C6400X RISC MICROPROCESSOR
FUNCTIONAL DESCRIPTION
MIPI HSI TX CONTROLLER PART
Finite State Machine
TxIDLE
Waiting ready
for next trans
Tx_ready&&
~fifo_empty
tx_end &&
~fifo_empty
TxBRK
Break frame
trans
break_done
frame_mode
&& br_frame
Tx_ready
&&fifo_empty
Tx
Data out
(include C-ID)
If(br_frame) :
clr_brframe active
~Ready
(Shift_cnt ==
data_2ndbit)
&& Ready
Figure 28-12 FSM of Tx module Part Block Diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
state_timeout
frame_mode
&& br_frame
IDLE
Tx module
sleeping
INT_fifo_empty : active
TxWAKE : inactive
~fifo_empty
fifo_empty
Ready
TxHOLD
Holding trans
ERR
Err_clr Error
generated
state_timeout
TxREQ
Wake up Rx &
Waiting ready
for new trans
TxWAKE : active
state_timeout
MIPI HSI
28-11