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S3C6400X RISC MICROPROCESSOR
CPUIF Status Mirrored Register (CPUIFC_MR_STAT)
Offset=0x20, R/W, Reset Value=0x0000_90A2
Field
Reserved
STAT
CPUIF Status1 Mirrored Register (CPUIFC_MR_STAT1)
Offset=0x24, R/W, Reset Value=0x0000_0002
Field
Reserved
STAT1
Bit
[31:16]
Reserved
[15:0]
Mirrored Protocol Register of STAT[15:0]
Bit
[31:16]
Reserved
[15:0]
Mirrored Protocol Register of STAT1[15:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
HOST INTERFACE
Initial State
0x0000
0x90A2
Initial State
0x0000
0x0002
24-23
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