Samsung S3C6400X User Manual page 997

UART
Peripheral BUS
31-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Transmitter
Transmit Buffer
Register(64 Byte)
Transmit Shifter
Control Buad-rate
Unit Generator
Receiver
Receive Shifter
Receive Buffer
Register(64 Byte)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Figure 31-1 UART Block Diagram
S3C6400 RISC MICROPROCESSOR
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Clock Source
Receive Holding Register
(Non-FIFO mode only)
Receive FIFO Register
(FIFO mode)
TXDn
RXDn