Samsung S3C6400X User Manual page 811

USB2.0 HS OTG
REGISTER MAP
OVERVIEW
The OTG PHY control registers based on address 7C10_0000h must be accessed to control and observe the
OTG PHY.
The OTG Link Core registers based on address 7C00_0000h is classified as follows:
— Core Global Registers
— Host Mode Registers
● Host Global Registers
● Host Port CSRs
● Host Channel-Specific Registers
— Device Mode Registers
● Device Global Registers
● Device Endpoint-Specific Registers
Only the Core Global and Host Port registers can be accessed in both Host and Device modes. When the OTG
Link is operating in either Device or Host mode, the application must not access registers from the other mode. If
an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register.
When the core switches from one mode to another, the registers in the new mode of operation must be
reprogrammed as they would be after a power-on reset.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-4
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR