Samsung S3C6400X User Manual page 838

S3C6400X RISC MICROPROCESSOR
receive status pop/read when the receive FIFO is empty and returns a value of 32'h0000_0000. The application
must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register
(GINTSTS.RxFLvl) is asserted.
HOST MODE RECEIVE STATUS DEBUG READ/STATUS READ AND POP REGISTERS
(GRXSTSR/GRXSTSP)
Register Address
GRXSTSR/ 0x7C00_001
C
GRXSTSP
0x7C00_0020
GRXSTSR/
GRXSTSP
[31:21]
PktSts [20:17]
DPID [16:15]
BCnt
ChNum
DEVICE MODE RECEIVE STATUS DEBUG READ/STATUS READ AND POP REGISTERS
(GRXSTSR/GRXSTSP)
Register Address
GRXSTSR/ 0x7C00_001
C
GRXSTSP
0x7C00_0020
R/W
R
Bit R/W
Reserved
RO Packet Status
Indicates the status of the received packet.
· 4'b0010 : IN data packet received
· 4'b0011 : IN transfer completed (triggers an
interrupt)
· 4'b0101 : Data toggle error (triggers an interrupt)
· 4'b0111 : Channel halted (triggers an interrupt)
· others : Reserved
RO Data PID
Indicates the Data PID of the received packet.
· 2'b00 : DATA0
· 2'b01 : DATA1
· 2'b10 : DATA2
· 2'b11 : MDATA
[14:4] RO Byte Count
Indicates the byte count of the received IN data
packet.
[3:0] RO Channel number
Indicates the channel number to which the current
received packet belongs.
R/W
R
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Host Mode Receive Status Debug Read/
Status Read and Pop Registers
Description
Description
Device Mode Receive Status Debug Read/
Status Read and Pop Registers
USB2.0 HS OTG
Reset Value
32 bits
Initial State
11'h0
4'b0
2'b0
11'h0
4'h0
Reset Value
32 bits
26-31