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DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
BRIEF OF THE SUB-BLOCK
The display controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR
includes programmable register sets and two-256x 25 palette memories. These are used to configure the display
controller. The VDMA is a dedicated display DMA. It can transfer the video data in frame memory to VPRCS. By
using this special DMA, the video data can be displayed on the screen without CPU intervention. The VPRCS
receives the video data from VDMA and sends the video data through the data ports (RGB_VD, VEN_VD, or
SYS_VD ) to the display device (LCD) after converting them into a suitable data format, for example 8-bit per pixel
mode (8 BPP Mode) or 16-bit per pixel mode (16 BPP Mode). The VTIME consists of programmable logic to
support the variable requirement of interface timing and rates commonly found in different LCD drivers. The
VTIME block generates RGB_VSYNC, RGB_HSYNC, RGB_VCLK, RGB_VDEN, SYS_CS1, SYS_CS0, etc.
Data Flow
FIFO is present in the VDMA. When FIFO is empty or partially empty, VDMA requests data fetching from the
frame memory based on the burst memory transfer mode(Consecutive memory fetching of 4 / 8 / 16 words per
one burst request without allowing the bus mastership to another bus master during the bus transfer). When this
kind of transfer request is accepted by bus arbitrator in the memory controller, there will be 4 /8 /16 successive
word data transfers from system memory to internal FIFO. The each size of FIFO is 64 words. The size of FIFO is
determined by the data transfer rate. The display controller has 8 FIFOs because it needs to support the overlay
window display mode. In case of one screen display mode, the only one FIFO must be used. The data through
FIFO is fetched by VPRCS which has a blending, scheduling function for the final image data. VPRCS supports
overlay function which enables to overlay any image up to 5 window images. Irrespective of the size it can be
blended with main window image with programmable alpha blending or color (chroma) key function. Figure 14-2
shows the data flow from system bus to the output buffer. VDMA has 5 DMA channels and 3 Local Input I/F. CSC
(Color Space Conversion) block changes YCbCr data to RGB data for the blending operation. Alpha values
written in SFR determine the level of blending. Data from Output buffer will be appearing to the Video Data Port.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-4
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR
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