Samsung S3C6400X User Manual page 72

S3C6400X RISC MICROPROCESSOR
Clock divider control register
S3C6400 has several clock dividers to support various operating clock frequency. The clock divider ratio can be
controlled by CLK_DIV0, CLK_DIV1, and CLK_DIV2.
REGISTER
CLK_DIV0
CLK_DVI1
CLK_DIV2
CLK_DIV0 mainly controls the system clocks and special clocks of multimedia IPs. The output frequencies of
APLL and MPLL are divided by ARM_RATIO and MPLL_RATIO. HCLKX2 clock is the base clock of other
operating system clocks and divided by HCLKX2_RATIO. There is operating frequency limitation. The maximum
operating frequency of HCLKX2, HCLK, and PCLK are 266MHz, 133MHz, and 66MHz, respectively. NAND,
SECUR, JPEG operating clock cannot exceed 66MHz. MFC and CAM operating clock cannot exceed 133MHz.
This operating clock condition must be met through CLK_DIV0 configuration.
User software must be care for the clock divider controlled by CLK_DIV0. Since the output frequency will be
varying during the clock ratio-changing period as shown in Figure 3-6.
CLK_DIV0
MFC_RATIO [31:28]
JPEG_RATIO [27:24]
CAM_RATIO [23:20]
SECUR_RATIO [19:18]
RESERVED [17:16] RESERVED
PCLK_RATIO [15:12]
HCLKX2_RATIO
HCLK_RATIO
RESERVED
MPLL_RATIO
RESERVED
ADDRESS R/W
0x7E00_F020 R/W
0x7E00_F024 R/W
0x7E00_F028 R/W
BIT
MFC clock divider ratio
CLKMFC = CLKMFC
JPEG clock divider ratio, which must be odd value. In other
words, S3C6400 supports only even divider ratio.
CLKJPEG = HCLKX2 / (JPEG_RATIO + 1)
CAM clock divider ratio
CLKCAM = HCLKX2 / (CAM_RATIO + 1)
Security clock divider ratio, which must be 0x1 or 0x3.
CLKSECUR = HCLKX2 / (SECUR_RATIO + 1)
PCLK clock divider ratio, which must be odd value. In other
words, S3C6400 supports only even divider ratio.
PCLK = HCLKX2 / (PCLK_RATIO + 1)
HCLKX2 clock divider ratio
[11:9]
HCLKX2 = HCLKX2
HCLK clock divider ratio
[8]
HCLK = HCLKX2 / (HCLK_RATIO + 1)
[7:5] RESERVED
DIV clock divider ratio
MPLL
[4]
DOUT = MOUT
MPLL
[3] RESERVED
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DESCRIPTION
Set clock divider ratio
Set clock divider ratio
Set clock divider ratio
DESCRIPTION
/ (MFC_RATIO + 1)
IN
/ (HCLKX2_RATIO + 1)
IN
/ (MPLL_RATIO + 1)
MPLL
SYSTEM CONTROLLER
RESET VALUE
0x0105_1000
0x0000_0000
0x0000_0000
RESET VALUE
0x0
0x1
0x0
0x1
0x1
0x1
0x0
0
0x0
0
0
3-27