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S3C6400X RISC MICROPROCESSOR
Memory port 0 CS selection
Set static memory chip selection multiplexing of memory port 0.
Setting for MP0_CS_SEL[0] and MP0_CS_SEL[2] are ignored. Distinguishing OneNANDC and
NFCON is done by XSELNAND pin value instead of MP0_CS_SEL[0] and MP0_CS_SEL[2].
When XSELNAND is 0, OneNANDC is selected. When XSELNAND is 1, NFCON is selected.
When NAND booting (XOM[4:3] = 00) is selected, the setting values of MP0_CS_SEL[1] and
MP0_CS_SEL[3] setting are ignored. Xm0CSn[2] and Xm0CSn[3] are used as NFCON CS0
and NFCON CS1. In this case, XSELNAND must be set to 1.
When OneNAND booting (XOM[4:1] = 0110) is selected, the setting values of MP0_CS_SEL[1]
and MP0_CS_SEL[3] setting are ignored. Xm0CSn[2] and Xm0CSn[3] are used as OneNANDC
CS0 and OneNANDC CS1. In this case, XSELNAND must be set to 0.
Xm0CSn[0]
Xm0CSn[1]
Xm0CSn[2]
Xm0CSn[3]
Xm0CSn[4]
Xm0CSn[5]
Independent Port for CFCON selection
0= CFCON uses shared interface of EBI.
1= CFCON uses independent interface.
CKE init value (SPCONSLP[4](0x7F0088B0))
0 = Initialization values of Xm0CKE of memory port 0 and Xm1CKE of memory port 1 are zero
when reset comes.
1 = Initialization values of Xm0CKE of memory port 0 and Xm1CKE of memory port 1 are one
when reset comes.
MP0_CS_SEL
[5]
[4]
[3]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
0
-
-
0
-
0
-
-
1
-
0
-
-
1
-
-
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XSELNAND
[2]
[1]
[0]
-
-
-
-
-
-
-
1
-
-
0
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MEMORY SUBSYSTEM
x
SROMC CS0
x
SROMC CS1
x
SROMC CS2
1
NFCON CS0
0
OneNANDC CS0
x
SROMC CS3
1
NFCON CS1
0
OneNANDC CS1
x
SROMC CS4
x
CFCON CS0
x
SROMC CS5
x
CFCON CS1
4-5
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