Samsung S3C6400X User Manual page 51

SYSTEM CONTROLLER
The lowest three bits of CLK_SRC register control the source clocks of three groups. When the bit has 0, then the
input clock is bypassed to the group. Otherwise, the PLL output will be applied to the group.
ARM and AXI/AHB/APB bus clock generation
ARM1176 processor of S3C6400X runs at up to 667MHz. The operating frequency can be controlled by the
internal clock divider, DIV
processor decreases the operating speed to reduce power dissipation.
S3C6400X consists of AXI bus, AHB bus, and APB bus to optimize the performance requirements. Internal IPs is
connected to appropriate bus systems to meet their I/O bandwidth and operating performance. When they are
attached to AXI bus or AHB bus, the operating speed can be up to 133MHz. While they are attached to APB bus,
the maximum operating speed can be up to 66MHz. Moreover, the bus speed between AHB and APB has high
dependency to synchronize data transmission. Figure 3-5 shows the part of bus clock generation to meet the
requirements of bus system clocks.
EXTCLK
1
XTIpll
0
HCLKX2 clocks are supplied to two DDR controllers, DDR0 and DDR1, of S3C6400X. The operating speed can
be up to 266MHz to send and to receive data through DDR controllers. Each HCLKX2 clock can be masked
independently to reduce redundant power dissipation on clock distribution network when the operation is not
required. All AHB bus clocks are generated from DIV
independently to reduce redundant power dissipation. HCLK_GATE register controls the mask operation of
HCLKX2 and HCLK.
Low-speed interconnection IPs transfer data through APB bus system. APB clocks of them are running at up to
66MHz as described in the above section and generated from DIV
PCLK_GATE register. As described, the frequency ratio between AHB clock and APB clock must be an even
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-6
Specifications and information herein are subject to change without notice.
, without any change of PLL frequency. The divider ratio varies from 1 to 8. ARM
ARM
MUX
APLL
0
1
APLL
CLK_SRC[0]
SYNCMUX
MUX
MPLL
1
0
0
1
OTHERS[6]
MPLL
CLK_SRC[1]
CLK_DIV0[15:12]
CLK_DIV0[27:24]
CLK_DIV0[19:18]
Figure 3-5. ARM and Bus clock generation
DIV
ARM
DIV
HCLKX2
CLK_DIV0[11:9]
DIV
CLK_DIV0[8]
DIV
DIV
DIV
clock divider. The generated clocks can be masked
HCLK
clock divider. They are also masked using
PCLK
S3C6400X RISC MICROPROCESSOR
HCLK_GATE[24:23]
HCLK
HCLK_GATE[29:25],
HCLK_GATE[22:0]
PCLK
PCLK_GATE[24:23]
CLKJPEG
SCLK_GATE[1]
CLKSECUR
SCLK_GATE[7]
ARMCLK
HCLKx2
HCLK
PCLK
CLKJPEG
CLKSECUR