Samsung S3C6400X User Manual page 912

HSMMC CONTROLLER
Complete interrupt in the Normal Interrupt Status register. If the Host Controller
cannot issue the command because of a command conflict error (Refer to
Command CRC Error) or because of Command Not Issued By Auto CMD12
Error, this bit shall remain 1 and the Command Complete is not set. Status issuing
Auto CMD12 is not read from this bit.
1 = Cannot issue command
0 = Can issue command using only CMD line
Note: Buffer Write Enable in Present register must not be asserted for DMA transfers since it generates Buffer
Write Ready interrupt
Power ON
Reset
Upper figure shows the state definitions of hardware that handles "Debouncing" .
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-36
Specifications and information herein are subject to change without notice.
Once debouncing
clock becomes valid
Figure 27-2. Card Detect State
S3C6400X RISC MICROPROCESSOR
SDCD#=1
Debouncing
SDCD#=0
Stable
Card Inserted
Stable
No Card