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S3C6400
RISC MICROPROCESSOR
32
This chapter describes the functions and usage of PWM TIMER in S3C6400X RISC microprocessor.
OVERVIEW
The S3C6400X RISC microprocessor comprises of five 32-bit timers. These timers are used to generate internal
interrupts to the ARM subsystem. In addition, Timers 0 and 1 include a PWM function (Pulse Width Modulation)
which can drive an external I/O signal. The PWM for timer 0 has an optional dead-zone generator capability,
which can be utilized to support a large current device. Timer 2, 3 and 4 are internal timers with no output pins.
The Timers are normally clocked off of a divided version of the APB-PCLK. Timers 0 and 1 share a
programmable 8-bit prescaler that provides the first level of division for the PCLK. Timer 2, 3, and 4 share a
different 8-bit prescaler. Each timer has its own, private clock-divider that provides a second level of clock
division (prescaler divided by 2,4,8, or 16). Alternatively, the Timers select a clock source from an external pin.
Timers 0 and 1 can select the external clock TCLK0. Timers 2, 3, and 4 can select the external clock TCLK1.
Each timer has its own 32-bit down-counter which is driven by the timer clock. The down-counter is initially
loaded from the Timer Count Buffer register (TCNTBn). When the down-counter reaches zero, the timer interrupt
request is generated to inform the CPU that the timer operation is completed. When the timer down-counter
reaches zero, the value of corresponding TCNTBn can be automatically reloaded into the down-counter to start
the next cycle. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the
timer running mode, the value of TCNTBn will not be reloaded into the counter.
The Pulse Width Modulation function (PWM) uses the value of the TCMPBn register. The timer control logic
changes the output level when the down-counter value matches the value of the compare register in the timer
control logic. Therefore, the compare register determines the turn-on time (or turn-off time) of a PWM output.
The TCNTBn and TCMPBn registers are double buffered to allow the timer parameters to be updated in the
middle of a cycle. The new values will not take effect until the current timer cycle completes.
A simple example of a PWM cycle is shown in the figure below
PWM TIMER
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Pulse Width Modulation Timer
32-1
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